Perl, Logic Design, Python, DFT Engineering, SV, Post Silicon Testing, Coverage metrics, Constrained random testing, Uvm, Profiling Tools, Architecture Verification

Scripting skills: Tcl, boundary scan , Vcs, System Verilog, Memory BIST, primetime, Logic Equivalency checking, Post-silicon validation and debug, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, EDA Tools, BIST architectures, Tessent tool sets, TestMax

Jtag, Dft, ATPG, Scan Insertion

Shell Scripting, Perl, Python, Tcl, Design Compiler, Verdi, ATPG Pattern Generation, RTL Netlist, primetime, JTAG Boundary Scan, Tessent Scan, Fault Coverage Analysis, Synopsys DFTMAX, Tessent ATPG, Tessent MBIST, Test Collateral, Siemens Tessent Tool Suite, Tessent Diagnosis, Scan Insertion, Scan Compression, MBIST Architecture Implementation

Jtag, MBIST, IEEE 1500, Diagnosis, Synopsys DFT tools, ATPG, LBIST, test compression, DFT architecture, Scan Insertion, Tessent

MBIST memory repair, MBIST pattern generation, Xcelium, power-aware DFT, SSN, simulation and debug, ATPG Scan, Tessent-based DFT, Tessent, non-timing simulations, Timing simulations, Advanced DFT, ATPG pattern generation, DRC violation debug fixes, LBIST, memory logic fault models, IJTAG, Retargetting coverage debug

Jtag, Shell, Python, Tcl, scan compression, IEEE 1149.x, automation infrastructure, automation and scripting, MBIST, DFT implementation methodology, IEEE 1687, DFT EDA tools, ATPG, Cad Methodology, hierarchical DFT methodologies, LBIST

boundary scan , Jtag, Perl, Shell scripting, Python, Tcl, Scan Insertion, MBIST, SMS and SEQ insertion, Multi-clock DFT architectures, Scan compression, Test clocks, Transition fault pattern generation, ATPG, Resets, DFT DRC debugging, Synopsys DFT tools, Coverage closure