DFT Engineer
DFT Engineer
leadic design pvt ltd4-8 Years
- Posted 21 hours ago
- Be among the first 10 applicants
Job Description
Required skill set:
Tessent-based DFT experience
ATPG pattern generation, Retargetting, coverage debug, DRC violation debug & fixes
Advanced DFT: IJTAG, SSN, LBIST, power-aware DFT
Timing and non-timing simulations and debug
MBIST pattern generation, simulation, and debug
ATPG, Scan, MBIST, memory repair (mandatory). Memory & logic fault models.
Tools: Tessent, Xcelium
Additional Details:
Experience: 4-8yrs, strong debugging skills with minimal or zero guidance
More Info
Key Skills
MBIST memory repair
MBIST pattern generation
Xcelium
power-aware DFT
SSN
simulation and debug
ATPG Scan
Tessent-based DFT
Tessent
non-timing simulations
Timing simulations
Advanced DFT
ATPG pattern generation
DRC violation debug fixes
LBIST
memory logic fault models
IJTAG
Retargetting coverage debug
About Company
Skills:
boundary scan , Perl, Tcl, test compression, scan compression, DFT signoff, pattern optimization, test access strategies, MBIST, DFT architecture definition, ATPG, yield ramp, LBIST, first silicon bring-up
Skills:
boundary scan , Vcs, Perl, System Verilog, Python, Tcl, primetime, Logic Equivalency checking, Jtag protocols, memory BIST, TetraMax, Gate level simulation debugging, Scan and BIST architectures, ATPG, EDA Tools, Tessent tool sets, TestMax
Skills:
automation, Scripting, scan compression, BSCAN, MBIST, Siemens Tessent, SSN TestKompress, DFT architecture, ATPG, EDA Tools, Synopsys TetraMAX, DFTMAX, LBIST, IJTAG
Skills:
boundary scan , Vcs, Perl, Python, System Verilog, Tcl, Memory BIST, primetime, Logic Equivalency checking, TetraMax, Scan and BIST architectures, JTAG protocols, ATPG, EDA Tools, Tessent tool sets, TestMax
Skills:
Eda, Shell, Jtag, Debugging, automation, Python, Scripting, Tcl, scan compression, IEEE 1149.x, automation infrastructure, CAD, MBIST, signoff flows, Dft, IEEE 1687, ATPG, Cad Methodology, hierarchical DFT methodologies, LBIST, implementation verification