C
DFT Engineer
C
- Posted 12 hours ago
- Be among the first 10 applicants
Job Description
Job Description
Lead DFT architecture and test strategy definition for advanced SoCs, ensuring high-quality manufacturing testability and diagnosis readiness.
Job Description - Grade Specific
Key Responsibilities
- Define SoC DFT architecture.
- Establish ATPG, scan, MBIST, LBIST strategies.
- Drive test coverage objectives.
- Define compression and diagnosis methodologies.
- Work with RTL, Verification, and Physical Design teams.
- Review DFT signoff requirements.
- Interface with customer test and manufacturing organizations.
Must Have
- 12+ years of DFT experience.
- Multiple successful SoC tapeouts.
- Good Knowledge on RISC and ARM SoC DFT strategy for sub-systems and top level
- Expertise in scan insertion and ATPG.
- Strong understanding of MBIST/LBIST.
- Experience with Tessent and/or Synopsys DFT tools.
- Knowledge of test compression and diagnosis.
- Understanding of JTAG and IEEE 1500/1687.
Good to Have
- Safety DFT.
- Automotive test methodologies.
- Silicon bring-up support experience.
- Yield learning and diagnosis.
- Chiplet test architecture.
- Advanced node test challenges.
More Info
Key Skills
IEEE 1500
Synopsys DFT tools
LBIST
test compression
DFT architecture
Tessent
About Company
Skills:
logic bist , Unix, Jtag, Perl, Linux, Tcl, scan diagnostics, Verilog RTL, silicon debug, back-annotated gate level verification, Scan compression and insertion, ATPG, at-speed test, Memory BIST and repair scheme implementation, IJTAG, Fault Simulation
Skills:
Embedded Software, Jtag, Technology, Hardware-VLSI, IDE/Compilers/Debuggers/SDK, LBIST, Design for Test
Skills:
Synopsys - Fusion compiler, Tessent - Testkompress, Scripting, test flows development, Design Compiler, Patterns re-targeting, DFX architecture of complex SOC, Scan ATPG patterns, SSN, IJTAG, TestKompress simulation and verification flow, IJTAG EDT, EDT SSN and SSH architecture
Skills:
boundary scan , Digital Logic Design, Jtag, Perl, Verilog, Loopback, Python, Tcl, DFT methodologies, Timing Analysis, MBIST, Siemens Tessent, circuit fundamentals, IEEE 1500, IEEE 1687, ATPG coverage analysis, compressed scan, Cadence Modus, Genus, SDF-based simulations
Skills:
test solutions, SoCs, DFT strategy, DFT architecture planning