DFT Engineer
DFT Engineer
smartsoc solutions pvt ltd5-7 Years
- Posted 15 hours ago
- Be among the first 10 applicants
Job Description
DFT Engineer – 5+ Years Experience
- 5+ years of hands-on experience in ASIC/SoC DFT implementation and verification.
- Strong expertise in Synopsys DFT tools, with mandatory hands-on experience in SMS and SEQ insertion.
- Strong experience in Scan insertion, Scan compression, DFT DRC debugging, and coverage closure.
- Hands-on experience with ATPG, including stuck-at and transition fault pattern generation and debugging.
- Good knowledge of MBIST, JTAG/Boundary Scan, test clocks, resets, and multi-clock DFT architectures.
- Proficiency in TCL/Perl/Python/Shell scripting and experience supporting DFT flows through tape-out.
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
SMS and SEQ insertion
Multi-clock DFT architectures
Scan compression
Test clocks
Transition fault pattern generation
Resets
DFT DRC debugging
Synopsys DFT tools
Coverage closure
About Company
Skills:
Shell Scripting, Perl, Python, Tcl, Design Compiler, Verdi, ATPG Pattern Generation, RTL Netlist, primetime, JTAG Boundary Scan, Tessent Scan, Fault Coverage Analysis, Synopsys DFTMAX, Tessent ATPG, Tessent MBIST, Test Collateral, Siemens Tessent Tool Suite, Tessent Diagnosis, Scan Insertion, Scan Compression, MBIST Architecture Implementation
Skills:
Jtag, Shell, Python, Tcl, scan compression, IEEE 1149.x, automation infrastructure, automation and scripting, MBIST, DFT implementation methodology, IEEE 1687, DFT EDA tools, ATPG, Cad Methodology, hierarchical DFT methodologies, LBIST
Skills:
scan compression, DFT architecture, ATPG, Scan Insertion, MBIST, Cadence DFT tools, test coverage analysis
Skills:
synopsys tools , MBIST Insertion Verification, ATPG Coverage Analysis Debug, Scan Insertion Compression, Boundary Scan Verification
Skills:
boundary scan , Perl, Tcl, test compression, scan compression, DFT signoff, pattern optimization, test access strategies, MBIST, DFT architecture definition, ATPG, yield ramp, LBIST, first silicon bring-up