Networking, Specman E, digital logic, Constrained-random verification, IP subsystem SoCs, Debug, Verification, systemverilog

Verilog, Python, Synopsys VCS, Cadence Incisive, formal verification, VHDL, Modelsim, Uvm

Tcl, Python, Perl, Shell, Debugging RTL verification issues, Assertions SVA, Functional Verification, UVM methodology, systemverilog, Coverage-driven verification

Verilog, Tcl, Python, Perl, Uvm, VHDL, systemverilog

Tcl, Python, Perl, Vcs, Uvm, Questa, systemverilog, Verdi

simvision , python, Cadence simulation tools, Uvm, Xcelium, netlist simulation