Senior Design Verification Engineer
Senior Design Verification Engineer
HCL TechBeeEarly Applicant
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Job Description
Design Verification Engineer (Senior Level - 10+ years experience)
Company: HCL Tech
Job Summary:
We are seeking a highly accomplished Design Verification Engineer (DV) to join our elite team and lead the verification efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of verification methodologies and the ability to drive the development and execution of comprehensive verification plans. You will be responsible for ensuring the functional integrity and quality of our next-generation integrated circuits through innovative verification strategies.
Responsibilities:
- Lead and define the overall verification strategy for assigned projects, leveraging advanced methodologies (UVM, Formal Verification)
- Architect and design robust verification environments (testbenches) to achieve exceptional code coverage and functional verification goals
- Utilize industry-leading verification tools (simulators, formal verification tools) to conduct thorough verification and analysis
- Debug and troubleshoot complex verification failures, identifying root causes and collaborating with design engineers for efficient resolution
- Mentor and guide junior DV engineers, fostering a culture of excellence and knowledge sharing within the team
- Champion best practices for verification code quality and participate in code reviews
- Stay at the forefront of the verification landscape by actively researching and adopting emerging tools and methodologies
- Provide technical leadership and contribute to the overall verification roadmap for the team
Qualifications:
- Master's degree in Electrical Engineering, Computer Engineering, or a related field (highly preferred)
- Minimum of 10+ years of experience in Design Verification for complex ASICs and SoCs
- Proven track record of successfully leading and executing verification projects
- In-depth knowledge of digital design principles, advanced verification methodologies (UVM, Formal Verification), and best practices
- Expertise in Verilog and VHDL with a strong grasp of coding styles and optimization techniques
- Extensive experience with a broad range of verification tools (simulators, formal verification tools, scripting languages)
- Excellent leadership, communication, collaboration, and problem-solving skills
- Ability to manage multiple projects, prioritize tasks, and meet aggressive deadlines
Benefits:
- Competitive salary and benefits package commensurate with experience and expertise
- Opportunity to lead and influence the verification of cutting-edge technologies
- Dynamic and challenging work environment with opportunities for professional growth and leadership development
- Recognition and rewards for outstanding contributions
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About Company
Skills:
Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV
Skills:
Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog
Skills:
test environments , SystemVerilog Assertions (SVA, Gate-Level Simulation (GLS, Test Cases, Uvm, formal verification, Coverage measures, Constrained-random verification environments, systemverilog, Low power debug, Verification methodologies, Formal tools, Verification test benches
Skills:
C, Perl, Python, Low power verification methods, FPGA emulator software environments, Emulation platforms, Uvm, systemverilog, Industry standard I/O interfaces, AMBA bus protocols, RTL development environments, Baremetal processor environments, Formal verification methods, UPF based low power verification, Transaction level modeling
Skills:
Tcl, Python, Perl, Shell, Debugging RTL verification issues, Assertions SVA, Functional Verification, UVM methodology, systemverilog, Coverage-driven verification