Senior Design Verification Engineer
Senior Design Verification Engineer
leadsoc technologies pvt ltd- Posted 2 months ago
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Job Description
Leadsoc is hiring!
Experience: 8 years to 13 years
Notice Period: Immediate to 15 days
Job Description:
- The ideal candidate will be taking part ownership of existing UVM based testbench for project and make required enhancements to the testbench as required.
- Develop testcases using the testbench. Create functional coverage items. Run code and functional coverage, analyse data and work with designer
- To achieve desired coverage. Make required updated to testbench for netlist simulation, run identified tests on netlist and work with team for required debug.
- Make required updates to testbench for netlist and gate-level simulation, run identified tests on netlist and gate-level netlist, and work with team for required debug.
Technical Skills:
- Well versed in full Verification cycle of including test development, debug and coverage closure through industry standard simulation tools.
- Well versed with Cadence simulation tools (Xcelium and Simvision) and netlist simulation.
- Familiarity with Datapath blocks is desirable.
- Knowledge of scripting – python/shell.
- Should be able to execute the tasks independently.
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About Company
Skills:
Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog
Skills:
SystemVerilog Assertions (SVA), test environments , Gate-Level Simulation (GLS), Test Cases, Low power debug, Constrained-random verification environments, Uvm, systemverilog, Verification test benches, Formal tools, Verification methodologies, Coverage measures, formal verification
Skills:
Vcs, Pcie, Python, Tcl, Xcelium, Uvm, systemverilog, APB, Questa, AXI4, AHB, SVA
Skills:
Regression Analysis, C, Ethernet Protocols, Python, RTL simulation, Uvm, systemverilog, constrained-random verification, testbench architecture, waveform debug, SoC Verification, assertions, functional coverage
Skills:
C, Perl, Python, Low power verification methods, FPGA emulator software environments, Emulation platforms, Uvm, systemverilog, Industry standard I/O interfaces, AMBA bus protocols, RTL development environments, Baremetal processor environments, Formal verification methods, UPF based low power verification, Transaction level modeling