Senior Design Verification Engineer
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Senior Design Verification Engineer: SOC Focused [Experience Level 10+]
Job Description
We are seeking a SoC Verification Engineer to work on end-to-end data-path verification for high-
performance ARM-based SoCs. This role focuses on validating correctness, coherency, performance,
and scalability of data movement across PCIe and CXL fabrics, from IP blocks through interconnect to
CPUs and memory, at chip and multi-chip system levels. This is full-chip, cross-IP, real-silicon mindset
verification.
Key Responsibilities
Validate cache coherency across multiple cores, agents, accelerators, across chip boundaries
Execute SoC-level DV plans for flows pertaining Cache Coherency and involving ARM
complexes in the flow path.
mplement system level stimulus for concurrent core/cache/dma/io traffic paths
Coherency across chip boundaries
Scalability testing:
N-chip configurations
Implement:
UVM-based system tests including mid-transaction reset, contention scenario
Scoreboards and data integrity checks under high throughput, concurrent traffic
Debug complex failures using:
Waveforms
Transaction traces
Firmware interaction
Collaborate with RTL, architecture, and firmware teams
Required Skills & Experience
Experience verifying ARM-based SoCs
Understanding of cache coherency (CHI / ACE preferred)
Proficiency in:
SystemVerilog / UVM
Transaction-level verification
Solid grasp of:
AXI / NoC architectures
DMA engines and memory systems
Preferred Qualifications
Multi-chip / chiplet system experience
Exposure to real workloads (storage, networking, AI accelerators)
Job ID: 145109739
Skills:
Verilog, Python, Synopsys VCS, Cadence Incisive, formal verification, VHDL, Modelsim, Uvm
Skills:
Computer Architecture, Vcs, DDR, Pcie, Perl, Ethernet, Python, Verdi, ARM-based SoC architecture, CHI, Xcelium, SystemVerilog UVM, Axi, APB, HBM, Questa, AHB, SVA
Skills:
testability , systemverilog, SoC IP verification methodologies, Uvm, DFX DFT concepts, ATPG, multi-level verification
Skills:
bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, full verification life cycle, vector processing units, industry-standard simulators, AI ML Accelerators, systemverilog, hierarchical memory subsystems, revision control systems, Specman E, constrained-random verification environments, Verification, IP subsystem SoCs, packet processing, congestion control, regression systems, Debug
Skills:
Tcl, Python, Perl, Shell, Debugging RTL verification issues, Assertions SVA, Functional Verification, UVM methodology, systemverilog, Coverage-driven verification
