Lead/Senior Design Verification Engineer

About the Role

We are seeking a highly skilled Design Verification Engineer with 8+ years of experience in functional verification and high-speed protocol verification. The ideal candidate will have proven hands-on experience with System Verilog, UVM, deep understanding of PCIe, USB, Ethernet/MAC, and AMBA protocols, and the ability to architect and execute robust verification strategies. In this role, you will work closely with design architects and cross-functional teams to ensure design correctness, compliance, and performance at block, subsystem, and SoC levels.

Key Responsibilities

• Develop and execute test plans for high-speed interfaces such as PCI, PCIe (Gen1–Gen5), USB (2.0/3.0), Ethernet (10/100/1G/10G), MAC, and AMBA protocols (APB, AHB-Lite, AXI).

• Architect and implement UVM-based verification environments for IPs, subsystems, and SoCs.

• Write, enhance, and maintain testbenches, monitors, checkers, assertions, and coverage models.

• Integrate and leverage Verification IPs (VIPs) to ensure compliance with protocol specifications.

• Perform coverage-driven and assertion-based verification (code, functional, and protocol compliance).

• Debug complex RTL issues, analyze simulation failures, and provide detailed bug reports.

• Drive coverage closure and ensure robust verification sign-off.

• Collaborate with architects and designers for design reviews, verification strategy, and performance validation.

• Contribute to automation of verification flows using Python, Perl, Tcl, or Shell scripting.