Senior Design Verification Engineer
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Senior Design Verification Engineer
Location: Bangalore.
Experience: 4 to 10 Years.
Notice Period: Any.
About Company:
ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.
Job ID: 144764827
Skills:
Jasper, Perl, Python, Asic verification, formal property checking tools, Synopsys Magellan, systemverilog, Cadence IEV, verification methodologies and tools, VC Formal, functional coverage, SVA
Skills:
Jasper, Perl, Python, Asic verification, verification methodologies, Synopsys Magellan, Uvm, systemverilog, Cadence IEV, VC Formal, functional coverage, SVA
Skills:
Verilog, Python, Synopsys VCS, Cadence Incisive, formal verification, VHDL, Modelsim, Uvm
Skills:
Usb, Ovm, Soc, DDR, Pcie, Ethernet, System Verilog, Ip, Uvm, Video, MIPI, VMM, ARM Based SoC Verification, HDMI, dsi, CSI
Skills:
Computer Architecture, Vcs, DDR, Pcie, Perl, Ethernet, Python, Verdi, ARM-based SoC architecture, CHI, Xcelium, SystemVerilog UVM, Axi, APB, HBM, Questa, AHB, SVA
