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Senior Design Verification Engineer
Location: Bangalore.
Experience: 4 to 10 Years.
Notice Period: Any.
About Company:
ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.
Job ID: 144764827
Skills:
Fpga, Perl, Python, object-oriented programming, RTL, emulation platforms, test plan development, Uvm, automation scripts, systemverilog
Skills:
Perl, Verilog, Python, Tcl, VHDL, Uvm, systemverilog
Skills:
Makefile, Perl, Ruby, Python, object-oriented programming, simulation debugging, power aware simulation, ASIC verification tools, Uvm, systemverilog, C-DPI, Axi, linting, AMBA, AHB
Skills:
bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, Specman E, hierarchical memory subsystems, Debug, IP subsystem SoCs, congestion control, regression systems, systemverilog, vector processing units, full verification life cycle, revision control systems, AI ML Accelerators, constrained-random verification environments, packet processing, Verification
Skills:
Computer Architecture, Debugging, Uvm, systemverilog, Coverage-Driven Verification, Constrained-Random Testing, formal verification, Functional Verification, Testbench Development, Verification Planning, Formal Tools, Rtl Design
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