cadence encounter , Unix Linux, SDC STA and Equivalence checking, Flow automation, Synopsys ICC2 tool set, Block SoC level Physical Design, PnR tools like ICC2 Innovus, SKILL Shell, 14nm 10nm 7nm 5nm process nodes, Tapeout sign-off experience, Python Script

Perl scripting, PrimeTime-SI, primetime, Antenna Checks, LVS, Substrate Bias, IR Drop Analysis, low power design, Physical Verification, Physical Design, Timing Closure, Synopsys Physical Design tools, Power Gating, Floor Planning, DRC, Voltage Islands

Physical Design, DFT Implementation, Layout Extraction, Rtl Design

Physical Design Engineer, Physical Design, Physical verification closure

Static Timing Analysis, Frontend, Asic, Timing Closure, Physical Verification

, Tcl, Perl, Fc, Routing, Python, Scripting, Synthesis, LEC, EDA Tools, Calibre, floorplanning, EMIR, ICV, Tempus, Placement, ERC, DRC, Power Planning, Genus, power analysis, Dc, LVS, Pt, pegasus, Physical Verification, Innovus, ICC2, formal verification

Tcl, PERL, Cadence, Floor Planning, SI Aware Routing, Synopsys, Voltage Islands, Timing Analysis Closure, ECO Tasks, Physical Verification, Timing Optimization, Substrate-bias Techniques, Asic Physical Design, Power Gating, Physical Design, Timing Closure on High Speed Interfaces, low power design, IR Drop Analysis, Antenna Checks, Signal Integrity Closure

Tcl, Python, PERL, Cerebrus, Synopsys Fusion Compiler, Cadence Innovus, Synthesis, physical verification tools, Place and Route workflows, Sta