FCFP, Physical Design, RTL

Routing, Full-chip dependencies, FCFP, Defs, Feed planning, Timing Closure, Tile floorplanning, PhyV, Placement, FCT, Timing, Shapes, Pins, EM-IR

power optimization , FPGA Design, floorplanning, Place And Route, Timing Analysis, DRC/LVS Checks, Signal Integrity, Physical Verification, RTL Synthesis, Circuit Layout

Routing, power analysis, Synthesis, EMIR, floorplanning, Placement, Physical Design Implementation, Power Planning

cadence encounter , Unix Linux, 14nm 10nm 7nm 5nm process nodes, SDC STA and Equivalence checking, Synopsys ICC2 tool set, PnR tools like ICC2 Innovus, Flow automation exposure, SKILL Shell, Tapeout sign-off experience, Python Script

Tcl, PERL, Cadence, Floor Planning, SI Aware Routing, Synopsys, Voltage Islands, Timing Analysis Closure, ECO Tasks, Physical Verification, Timing Optimization, Substrate-bias Techniques, Asic Physical Design, Power Gating, Physical Design, Timing Closure on High Speed Interfaces, low power design, IR Drop Analysis, Antenna Checks, Signal Integrity Closure