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Physical Design Engineer
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- Posted 8 hours ago
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Job Description
Description
We are seeking an experienced Physical Design Engineer to join our team in India. The ideal candidate will have a strong background in physical design implementation and will be responsible for optimizing IC layouts to meet performance and power requirements.
Responsibilities
- Perform physical design implementation of integrated circuits (ICs) from RTL to GDSII.
- Develop and optimize physical layouts for performance, power, and area.
- Conduct design rule checks (DRC) and layout versus schematic (LVS) verification.
- Collaborate with design engineers to resolve issues related to physical design.
- Utilize EDA tools for various stages of the physical design flow, including synthesis, place and route, and timing analysis.
- Engage in design reviews and provide feedback to ensure adherence to design specifications.
Skills and Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- 6-15 years of experience in physical design engineering or a related field.
- Proficiency in using EDA tools such as Cadence, Synopsys, or Mentor Graphics.
- Strong understanding of VLSI design principles and physical design methodologies.
- Experience with RTL synthesis and timing closure techniques.
- Familiarity with scripting languages such as Tcl, Perl, or Python for automation.
- Excellent problem-solving skills and attention to detail.
- Ability to work collaboratively in a team environment.
Bachelor Of Technology (B.Tech/B.E), Masters in Technology (M.Tech/M.E)
More Info
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Key Skills
About Company
Skills:
Place and route (PnR), System on Chips (SoCs), Static Timing Analysis (STA), Unified Power Format (UPF), Deep sub-micron technology, Multi-voltage domains, Physical design methodologies, Circuit Design, Power gating, IP integration, Netlist2GDS, ASIC design flows, Sign-off optimizations, Multiple technology nodes in advanced processes, device physics, Floorplan, Sign-off convergence, Lower technology nodes, Low power design implementation
Skills:
power optimization , Routing, Logic Design, Perl, Python, Tcl, Circuit Design, floorplanning, Mentor, Cadence, Signal Integrity, LVS, Digital Design Fundamentals, Physical Verification, Physical Design, ERC, Placement, Timing Closure, DRC, Timing, EDA Tools, Synopsys, Rtl Design
Skills:
Clock Planning, Physical Verification, floorplanning, Timing Closure, Placement and Routing, Physical Design Implementation
Skills:
Block level and Top-level physical implementation, Place and Route processes, Physical Design, Synthesis for high-speed designs
Skills:
Static Timing, Routing, Physical Verification, Synthesis, Power Efficiency, Custom Clocking, Physical Design, Placement, floorplanning, Formal Equivalency, IR-Drop