Physical Design Engineer
Physical Design Engineer
QTiMinds Private LimitedEarly Applicant
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Job Description
6-9 Years Experience in Physical design (FCFP)
Critical Tile Exp - PD and Timing
Exp with critical tiles handling - challenges of floorplan/Placement/Routing/Timing/EM-IR/PhyV/FCT
Understanding dependencies - RTL/FCFP/PD/Timing/PV etc
Lead for a group of tiles Execution for convergence FCFP - Exp (Handling Defs/Shapes/Pins and feed planning with FCFP) for the tiles cluster Full Chip understanding and exposure will be add-on
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Key Skills
About Company
Skills:
Routing, Physical Verification, Physical Design, EDA Tools, floorplanning, Placement, Timing Closure, DRC, LVS
Skills:
power optimization , FPGA Design, floorplanning, Place And Route, Timing Analysis, DRC/LVS Checks, Signal Integrity, Physical Verification, RTL Synthesis, Circuit Layout
Skills:
EM), Power integrity analysis (IR drop, Antenna), Physical verification (DRC, Static Timing Analysis (STA), Routing, Mentor Calibre, VLSI design principles, LVS, Physical design methodologies, floorplanning, Cadence Innovus, Synopsys Fusion Compiler, Semiconductor physics, Timing closure techniques, Design Verification, RTL synthesis, Placement, Deep sub-micron process technologies
Skills:
Block level and Top-level physical implementation, Place and Route processes, Physical Design, Synthesis for high-speed designs
Skills:
Routing, power analysis, Synthesis, EMIR, floorplanning, Placement, Physical Design Implementation, Power Planning