Senior Physical Design Engineer
- Posted 2 months ago
- Be among the first 10 applicants
Job Description
- 4+ years of experience in Physical Design Implementation
- Perform block level physical implementation tasks from RTL to GDSII including synthesis, floorplanning, power planning, placement, Clock Tree Synthesis (CTS) and routing.
- Proven track record with advanced nodes of 3nm/4nm/5nm/7nm with successful tapeouts
- Perform sign-off analysis and closure on Static Timing Analysis (STA), formal verification (LEC), power analysis (EMIR), and physical verification (DRC/LVS/ERC) for tapeout.
- Optimize designs for Performance, Power, and Area (PPA) by improving congestion, timing, and power consumption.
- Experience with EDA tools in DC/Genus, ICC2/FC/Innovus, PT/Tempus, Calibre/ICV/Pegasus.
- Proficient in scripting with Tcl and Perl/Python
More Info
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Key Skills
EMIR
Physical Design Implementation
About Company
Skills:
Routing, Physical Verification, Physical Design, EDA Tools, floorplanning, Placement, Timing Closure, DRC, LVS
Skills:
Block level and Top-level physical implementation, Place and Route processes, Physical Design, Synthesis for high-speed designs
Skills:
Block level and Top-level physical implementation, Place and Route processes, Synthesis for high-speed designs, Physical Verification, Physical Design for complex Chiplets, Unix/Linux environment
Skills:
static timing analysis, routing, Innovus, LVS, Parasitic Extraction, Fusion Compiler, DRC, Placement, floorplanning, Clock Tree Synthesis, ICC2
Skills:
Block level and Top-level physical implementation, Place and Route processes, Synthesis for high-speed designs, Physical Verification, Physical Design for complex Chiplets, Unix/Linux environment