4+ years of experience in Physical Design Implementation
Perform block level physical implementation tasks from RTL to GDSII including synthesis, floorplanning, power planning, placement, Clock Tree Synthesis (CTS) and routing.
Proven track record with advanced nodes of 3nm/4nm/5nm/7nm with successful tapeouts
Perform sign-off analysis and closure on Static Timing Analysis (STA), formal verification (LEC), power analysis (EMIR), and physical verification (DRC/LVS/ERC) for tapeout.
Optimize designs for Performance, Power, and Area (PPA) by improving congestion, timing, and power consumption.
Experience with EDA tools in DC/Genus, ICC2/FC/Innovus, PT/Tempus, Calibre/ICV/Pegasus.
