Search by job, company or skills

Senior Physical Design Engineer

Senior Physical Design Engineer

ALTEN Calsoft Labs
5-7 Years
Not Disclosed
  • Posted 21 hours ago
  • Be among the first 10 applicants

Job Description

ACL Digital (Hyderabad)

We are looking for a Physical Design Expert with 5+ years of experience to lead execution for critical tiles. In this role, you will handle tile floorplanning, placement, routing, timing closure, EM-IR, PhyV, and FCT while driving cross-functional convergence.

Key Requirements:Experience in PD amp; Timing with expertise in critical tile handling.

Technical Skills: Hands-on experience with FCFP (Defs, Shapes, Pins, and Feed planning) amp; full-chip dependencies.Leadership: Ability to act as a Cluster Lead for a group of tiles to achieve execution convergence.

Location: Hyderabad | Notice Period: 0–30 Days (Immediate joiners preferred).

Interested Send your updated resume to [Confidential Information] today!

More Info

Job Type:
Industry:
Employment Type:

Key Skills

Full-chip dependencies

FCFP

Defs

Feed planning

Tile floorplanning

PhyV

FCT

Shapes

Pins

EM-IR

About Company

Similar Jobs

4-8 yrs
Hyderabad, India
Skills:
static timing analysis, routing, Perl, Python, Tcl, Innovus, Fusion Compiler, floorplanning, ICC2, LVS, DRC, Placement, Parasitic Extraction, Clock Tree Synthesis
4-6 yrs
Hyderabad, India
Skills:
Mentor-Calibre, Physical Verification, pegasus, Cadence Innovus, EM IR drop analysis, Static Dynamic IR analysis, EDA tool automation, Voltus
3-5 yrs
Hyderabad, India
Skills:
power optimization , Eda, Tcl Scripting, Python, power analysis, Sta, Agentic AI methodologies, DVFS, LEC, AI-driven optimization, Place And Route, UPF, Physical Verification, Timing Power closure, Asic Physical Design, Physical Verification, full chip and block level floor-planning, Eco, multi-Vt power domains, RTL to GDS Flow, CPF, LLM-assisted debugging, autonomous agents
8-12 yrs
Hyderabad, India
Skills:
Routing, Python, Tcl, CTS, floorplanning, Placement Optimization, Antenna Density, LVS, Power Planning, IC Validator, Calibre, Physical Verification, Signoff Closure, Physical Design, ERC, Timing Closure, ECO Implementation, DRC