Lead Physical Design Engineer with PnR (Placement & Routing)

Company Description

MosChip® Technologies is a publicly traded company specializing in Silicon and Product Engineering solutions, boasting a team of over 1,300 engineers across Silicon Valley, USA, and India. The company provides comprehensive engineering solutions, including silicon design, verification, systems, software, device engineering, and AI/ML solution design, along with test automation, Digital IP, Verification IP, and Mixed Signal IP development. With an impressive record of delivering 200+ SoC tape-outs and millions of connectivity ICs, MosChip® has a proven track record of first-time right silicon.

Role Description

This is a full-time role for a Lead Physical Design Engineer with a focus on Placement & Routing (PnR), located on-site in Hyderabad. The Lead Physical Design Engineer will be responsible for managing and overseeing the physical design process, including placement, routing, and physical verification. Daily tasks will include collaborating with cross-functional teams, creating and validating physical designs, ensuring design quality, and meeting project timelines. Additionally, the engineer will troubleshoot and resolve issues related to physical design processes.

Qualifications

• He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
• Minimum of 6-15 years of experience in physical design.
• He/She should have worked on 7nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.
• Provide technical guidance, mentoring to physical design engineers.
• Lead a team of Physical design engineers and be responsible for their blocks closure
• Interface with front-end ASIC teams to resolve issues.
• Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.
• Expertise in Timing closure on high speed interfaces is a plus
• Excellent communication skills.
• Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
• Extensive experience and detailed knowledge in Cadence or Synopsys.
• Expertise in scripting languages such as PERL, TCL.
• Strong Physical Verification skill set.
• Static Timing Analysis in Primetime or Primetime-SI.
• Good written and oral communication skills. Ability to clearly document plans.
• Ability to interface with different teams and prioritize work based on project needs.