Senior Physical Design Engineer
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Job Description – Physical Design Engineer
ACL Digital is hiring experienced Physical Design Engineers for our growing VLSI team.
Position
Physical Design Engineer
Experience: 6+ Years
Job Locations
Job Responsibilities
Required Skills
Qualification
Notice Period: Immediate to 30 days preferred
Interested candidates can share their updated resume to: [[Confidential Information]]
#Hiring #PhysicalDesign #ASIC #VLSI #Semiconductor #ICC2 #Innovus #STA #ACLdigital
Job ID: 148676027
Skills:
redhawk , Python, Perl, Tcl, Sta, Multi-voltage domains, primetime, Foundry PDKs, Tempus, Cadence, Cadence Innovus, Power gating, UPF, Voltus, Implementation tool suite, SDC, Signoff tools, EDA Tools, Physical Design, TSMC, Samsung, CPF, Synopsys, Synopsys ICC2, Low-power design techniques, Timing Analysis
Skills:
static timing analysis, industry-standard EDA tools for physical design and verification, Synthesis, RTL-to-GDS workflows, multi-power domain analysis, Place And Route, low-power design techniques, Clock Tree Synthesis
Skills:
Static Timing, Routing, Physical Verification, Synthesis, Power Efficiency, Custom Clocking, Physical Design, Placement, floorplanning, Formal Equivalency, IR-Drop
Skills:
layout verification , Computer Engineering, System Verilog, Tcl, low-power designs, Electrical Engineering, Computer Science, design rules, Vlsi Design
Skills:
ECO Change Order, power integrity , Routing, Timing Optimization, EMIR Analysis, LVS, Cadence Innovus, Physical Verification, floorplanning, Physical Design, Crosstalk Analysis, Signal Integrity Closure, DRC
