Senior Physical Design Engineer
Senior Physical Design Engineer
ALTEN Calsoft Labs6-8 Years
- Posted a month ago
- Be among the first 10 applicants
Job Description
Job Description – Physical Design Engineer
ACL Digital is hiring experienced Physical Design Engineers for our growing VLSI team.
Position
Physical Design Engineer
Experience: 6+ Years
Job Locations
- Bengaluru
- Hyderabad
- Chennai
Job Responsibilities
- Handle complete ASIC Physical Design flow from Netlist to GDSII
- Perform Floorplanning, Placement, CTS, Routing, and Physical Verification
- Timing closure and optimization for setup/hold violations
- Work on power planning, IR drop analysis, and congestion analysis
- Perform STA and ECO implementation
- Collaborate with RTL, DFT, and Signoff teams for successful tapeout
- Ensure design quality and adherence to project timelines
Required Skills
- Strong expertise in Physical Design flow
- Hands-on experience with:
- ICC2 / Innovus
- PrimeTime / Tempus
- Fusion Compiler (preferred)
- Good understanding of:
- STA
- Low Power Design
- Physical Verification
- MMMC concepts
- UPF/CPF
- Scripting knowledge in Tcl/Perl/Python is an added advantage
Qualification
- B.E / B.Tech / M.E / M.Tech in Electronics or related field
Notice Period: Immediate to 30 days preferred
Interested candidates can share their updated resume to: [[Confidential Information]]
#Hiring #PhysicalDesign #ASIC #VLSI #Semiconductor #ICC2 #Innovus #STA #ACLdigital
More Info
Key Skills
Physical Design flow
UPF
Fusion Compiler
Innovus
ICC2
Tempus
MMMC concepts
About Company
Skills:
power optimization , Routing, Logic Design, Perl, Python, Tcl, Circuit Design, floorplanning, Mentor, Cadence, Signal Integrity, LVS, Digital Design Fundamentals, Physical Verification, Physical Design, ERC, Placement, Timing Closure, DRC, Timing, EDA Tools, Synopsys, Rtl Design
Skills:
Perl, Python, Tcl, Innovus, Calibre, Assura, ICC2, Cadence, ICV, Synopsys
Skills:
routing, Sta, CTS, ECO execution, Pv, floorplanning, Dfm, constraints synthesis, Dft, Si, Timing Closure, block-level PnR, Netlist to GDS flow
Skills:
C, Tcl, Routing, Perl, Physical Verification, LEC, Calibre, Innovus, floorplanning, EDA Tools, Clock Planning, ICC2, primetime, Placement, Timing Closure, Physical Design Implementation
Skills:
Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology