Senior Physical Design Engineer
Senior Physical Design Engineer
ALTEN Calsoft Labs- Posted a month ago
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Job Description
Job Description – Physical Design Engineer
ACL Digital is hiring experienced Physical Design Engineers for our growing VLSI team.
Position
Physical Design Engineer
Experience: 6+ Years
Job Locations
- Bengaluru
- Hyderabad
- Chennai
Job Responsibilities
- Handle complete ASIC Physical Design flow from Netlist to GDSII
- Perform Floorplanning, Placement, CTS, Routing, and Physical Verification
- Timing closure and optimization for setup/hold violations
- Work on power planning, IR drop analysis, and congestion analysis
- Perform STA and ECO implementation
- Collaborate with RTL, DFT, and Signoff teams for successful tapeout
- Ensure design quality and adherence to project timelines
Required Skills
- Strong expertise in Physical Design flow
- Hands-on experience with:
- ICC2 / Innovus
- PrimeTime / Tempus
- Fusion Compiler (preferred)
- Good understanding of:
- STA
- Low Power Design
- Physical Verification
- MMMC concepts
- UPF/CPF
- Scripting knowledge in Tcl/Perl/Python is an added advantage
Qualification
- B.E / B.Tech / M.E / M.Tech in Electronics or related field
Notice Period: Immediate to 30 days preferred
Interested candidates can share their updated resume to: [[Confidential Information]]
#Hiring #PhysicalDesign #ASIC #VLSI #Semiconductor #ICC2 #Innovus #STA #ACLdigital
More Info
Key Skills
Physical Design flow
Fusion Compiler
ICC2
Tempus
UPF
Innovus
MMMC concepts
About Company
Skills:
Perl, Python, Tcl, Innovus, primetime, Calibre, StarRC, ICC2, Voltus
Skills:
Routing, floorplanning, Sta, CTS, primetime, Fusion Compiler, ICC2, Innovus, PNR, Physical Design, Placement, Timing Closure, Sign-off
Skills:
C, Perl, Tcl, C++, Routing, Clock Planning, Physical Verification, floorplanning, Timing Closure, Physical Design Implementation, Innovus, Calibre, primetime, Placement, ICC2, LEC, EDA Tools
Skills:
power integrity , Routing, Synthesis, Multi-Voltage Domains, Sign-off, Physical Design implementation, Placement, Low-Power Design, Physical Verification, Timing Closure, floorplanning, CTS
Skills:
Tcl, Routing, Perl, 28nm and lower technology nodes, Timing Constraints, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, Methodologies, CTS, Innovus, Sta, ICC2, Tk, Placement, Timing Closure, PT-PX, sub-micron technology, Netlist2GDSII Implementation