Senior Physical Design Engineer
Senior Physical Design Engineer
Globex Digital Corp- Posted 3 months ago
- Be among the first 10 applicants
Job Description
Experience - 7+years
Location - Pan India
NP - Immediate to 60 Days
JD Physical Design -
- In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification.
- Should have experience on Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes.
- Should have experience on programming in Tcl/Tk/Perl.
- Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre).
- Well versed with timing constraints, STA and timing closure.
- Inspirational leadership style, good communication skills, and ability to work in a global environmentIn-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification
- Should have experience on Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes.
- Should have experience on programming in Tcl/Tk/Perl · Well versed with timing constraints, STA and timing closure.
- Inspirational leadership style, good communication skills, and ability to work in a global environment.
More Info
Key Skills
28nm and lower technology nodes
Power Integrity Analysis
Calibre
CTS
Innovus
ICC2
PT-PX
sub-micron technology
Netlist2GDSII Implementation
About Company
Skills:
Perl, Python, Tcl, Innovus, primetime, Calibre, StarRC, ICC2, Voltus
Skills:
Routing, floorplanning, Sta, CTS, primetime, Fusion Compiler, ICC2, Innovus, PNR, Physical Design, Placement, Timing Closure, Sign-off
Skills:
power integrity , Perl, Python, Tcl, physical design sign-off, static dynamic IR drop, physical ECOs, Cadence Voltus, electromigration, power-grid optimization, PG strengthening, Ansys RedHawk, EM IR analysis, vectorless EM IR analysis
Skills:
power integrity , Routing, Synthesis, Multi-Voltage Domains, Sign-off, Physical Design implementation, Placement, Low-Power Design, Physical Verification, Timing Closure, floorplanning, CTS
Skills:
static timing analysis, Perl, Tcl, Synthesis, Makefile scripting, physical design CAD flow, Mentor Calibre, Power Distribution, hierarchical P&R, Cadence Innovus, Cadence Genus, Floor Planning, physical design verification