Senior Physical Design Engineer
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Job Description
Key Requirements:
5 to 10+ years of hands-on experience in block and sub-system level Physical Design implementation
Experience with the latest process nodes
Strong knowledge of the complete PD flow: Synthesis, Floorplanning, Placement, CTS, Routing & Sign-off
Expertise in Timing Closure, Low-Power Design & Multi-Voltage Domains
Experience with sign-off closure for Timing, Power Integrity & Physical Verification
Ability to lead, mentor and provide technical guidance to team members on complex issues
More Info
Job Type:
Industry:
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Key Skills
CTS
Sign-off
Multi-Voltage Domains
Physical Design implementation
Low-Power Design
About Company
Skills:
Python, Tcl, floorplanning, Physical design flows, Clock CTS, Logical Equivalence, Synthesis, Timing Analysis, EDA Tools, Budgeting, Physical Verification DRC LVS ERC, Place And Route
Skills:
Routing, floorplanning, Sta, CTS, primetime, Fusion Compiler, ICC2, Innovus, PNR, Physical Design, Placement, Timing Closure, Sign-off
Skills:
C, Perl, Tcl, C++, Routing, Clock Planning, Physical Verification, floorplanning, Timing Closure, Physical Design Implementation, Innovus, Calibre, primetime, Placement, ICC2, LEC, EDA Tools
Skills:
Perl, Python, Tcl, Physical Design flow, Sta, primetime, Fusion Compiler, ICC2, Tempus, UPF, Innovus, low power design, MMMC concepts, Physical Verification, CPF
Skills:
Tcl, Python, PERL, ECO Timing Closure, Synthesis, Layout Closure, Block-level and Full-chip Floor-planning, primetime, Ir, Physical Verification, Innovus, CTS, Sta, ICC2, Physical Design, Tempus, RTL2GDSII flow, Seahawk, Place And Route, Timing Convergence, High Frequency Design Methodologies