Senior Physical Design Engineer
Senior Physical Design Engineer
BitSilica5-10 Years
- Posted 2 hours ago
- Be among the first 10 applicants
Job Description
Key Requirements:
5 to 10+ years of hands-on experience in block and sub-system level Physical Design implementation
Experience with the latest process nodes
Strong knowledge of the complete PD flow: Synthesis, Floorplanning, Placement, CTS, Routing & Sign-off
Expertise in Timing Closure, Low-Power Design & Multi-Voltage Domains
Experience with sign-off closure for Timing, Power Integrity & Physical Verification
Ability to lead, mentor and provide technical guidance to team members on complex issues
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
CTS
Low-Power Design
Sign-off
Multi-Voltage Domains
Physical Design implementation
About Company
Skills:
clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, PNR Floor Plan, Power Mesh, Timing Signoff
Skills:
Tcl, Python, PERL, Seahawk, Synthesis, ECO Timing Closure, Layout Closure, Block-level and Full-chip Floor-planning, primetime, Physical Verification, Ir, CTS, Innovus, Sta, ICC2, Physical Design, Tempus, RTL2GDSII flow, Place And Route, Timing Convergence, High Frequency Design Methodologies
Skills:
Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology
Skills:
C, Perl, Tcl, Physical Verification, Clock Planning, Placement and Routing, floorplanning, Timing Closure, Physical Design Implementation
Skills:
Python, Tcl, floorplanning, Physical design flows, Logical Equivalence, Clock CTS, Synthesis, Timing Analysis, EDA Tools, Budgeting, Physical Verification DRC LVS ERC, Place And Route