Perl, Python, Tcl, Innovus, primetime, Calibre, StarRC, ICC2, Voltus

Routing, floorplanning, Sta, CTS, primetime, Fusion Compiler, ICC2, Innovus, PNR, Physical Design, Placement, Timing Closure, Sign-off

C, Perl, Tcl, C++, Routing, Clock Planning, Physical Verification, floorplanning, Timing Closure, Physical Design Implementation, Innovus, Calibre, primetime, Placement, ICC2, LEC, EDA Tools

power integrity , Routing, Synthesis, Multi-Voltage Domains, Sign-off, Physical Design implementation, Placement, Low-Power Design, Physical Verification, Timing Closure, floorplanning, CTS

Tcl, Routing, Perl, 28nm and lower technology nodes, Timing Constraints, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, Methodologies, CTS, Innovus, Sta, ICC2, Tk, Placement, Timing Closure, PT-PX, sub-micron technology, Netlist2GDSII Implementation

static timing analysis, Perl, Tcl, Synthesis, Makefile scripting, physical design CAD flow, Mentor Calibre, Power Distribution, hierarchical P&R, Cadence Innovus, Cadence Genus, Floor Planning, physical design verification

Place and Route (P&R), Python, Tcl, RTL-to-GDSII flow, Synthesis, Physical Design, Genus, Post-route signoff, ICC2, Synopsys Fusion Compiler, Cadence Innovus

hardware engineering , Static Timing Analysis (STA), Automation, Deep sub-micron technology, Multi-voltage domains, Circuit Design, Power gating, UPF, Physical Design, Synthesis, ASIC design flows, Sign-off optimizations, PNR, device physics, Low power design implementation

layout verification , Design For Testing (DFT), System on a Chip (SoC), Very Large Scale Integration (VLSI) design, Computer Engineering, System Verilog, ASIC Design, Electrical Engineering, Computer Science, Low power designs, Design rules