Senior Physical Design Engineer
Senior Physical Design Engineer
ALTEN Calsoft Labs- Posted 13 hours ago
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Job Description
WE ARE HIRING: Senior Physical Design Engineer
ACL Digital is expanding its Semiconductor/VLSI practice in Bengaluru! We are looking for an experienced Physical Design Engineer with 5+ years of hands-on expertise to drive full-flow RTL-to-GDSII execution on advanced technology nodes.
Key Role Details:
- Role: Physical Design Engineer
- Experience Required: 5+ Years
- Location: Bengaluru, Karnataka
- Notice Period:Immediate to 30 Days ONLY
Key Responsibilities:
- Lead Netlist-to-GDSII flow including Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, and Timing Closure (STA).
- Execute Static Timing Analysis (STA), cross-talk noise analysis, power network analysis (IR-drop/EM), and Physical Verification (DRC/LVS/ERC).
- Hands-on work on lower-node designs (e.g., 7nm / 5nm / 3nm).
- Collaborate with Front-End, DFT, and Package design teams for successful tape-out execution.
Tech Stack / Requirements:
- Proven expertise in standard industry EDA tools (Innovus, ICC2, Primetime, Calibre, Voltus/StarRC).
- Strong understanding of low-power design methodologies (UPF/CPF, Clock Gating, Multi-VT).
- Excellent scripting skills in Tcl, Perl, or Python for flow automation.
How to Apply:
Interested candidates with a notice period of 30 days or less, please share your updated CV to [Confidential Information]
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About Company
Skills:
C, Perl, Tcl, C++, Routing, Clock Planning, Physical Verification, floorplanning, Timing Closure, Physical Design Implementation, Innovus, Calibre, primetime, Placement, ICC2, LEC, EDA Tools
Skills:
Tcl, Python, Logical Equivalence, Synthesis, Timing Analysis, Physical Verification DRC LVS ERC, Physical design flows, Place And Route, EDA Tools, Budgeting, floorplanning, Clock CTS
Skills:
Perl, Python, Tcl, Physical Design flow, Sta, primetime, Fusion Compiler, ICC2, Tempus, UPF, Innovus, low power design, MMMC concepts, Physical Verification, CPF
Skills:
Tcl, Python, PERL, ECO Timing Closure, Synthesis, Layout Closure, Block-level and Full-chip Floor-planning, primetime, Ir, Physical Verification, Innovus, CTS, Sta, ICC2, Physical Design, Tempus, RTL2GDSII flow, Seahawk, Place And Route, Timing Convergence, High Frequency Design Methodologies
Skills:
Tcl, Routing, Perl, 28nm and lower technology nodes, Timing Constraints, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, Methodologies, CTS, Innovus, Sta, ICC2, Tk, Placement, Timing Closure, PT-PX, sub-micron technology, Netlist2GDSII Implementation