Senior Design Verification Engineer

Role Overview

You will be responsible for SoC and IP-level verification, working across multiple projects and environments.

Success in this role means:

You independently drive verification from plan to closure

You debug complex issues across RTL, testbench, and system level

You contribute to first-time-right silicon

Key Responsibilities

• Develop and execute verification plans for SoC and IP blocks

• Build and enhance SystemVerilog / UVM-based testbenches

• Write C-based tests for embedded cores (ARM / RISC-V / ARC)

• Drive functional and code coverage closure

• Debug complex issues across RTL, protocols, and verification environments

• Work closely with Design, Architecture, Firmware, and Software teams

• Support FPGA-based verification / RTL bring-up when required

• Contribute to improving verification methodologies and reuse

Required Skills (Must Have)

• 4+ years of hands-on Design Verification experience

• Strong expertise in SystemVerilog and UVM

• Solid experience in SoC and/or IP verification

• Protocol knowledge: AXI, APB, I2C, UART, PCIe, DDR

• Strong debugging and problem-solving skills

• Experience with coverage-driven verification and closure

• Ability to work independently and in cross-functional teams

Good to Have

• Experience in FPGA prototyping / emulation

• Exposure to multiple SoC platforms or client projects

• Mentoring or leading verification tasks

Job Details

Role: Design Verification Engineer (SoC + IP)

Company: Interex Semiconductor

Location: Bengaluru (On-site)

Experience: 4–10 Years

Notice Period: 0–60 Days preferred

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