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Hi All,
ACL Digital is hiring Design Verification Engineers
Experience: 8+ years
Location: Hyderabad / Bangalore
Join: Immediate
Key Skills:
10+ Years in IP/Sub-System/SoC DV Testbench Development
Strong in SV UVM, Functional & Formal Verification
Hands-on with RISC-V / CPU / PCIe / DDR / Ethernet
SoC Integration, Debugging & Coverage Closure
Expertise in Assertions & Complex Verification Flows
Thanks,
K Himabindu
Job ID: 144750925
Skills:
scoreboard , System Verilog, verification environment, verification closure, script development, interface agents, Uvm, testbench components
Skills:
DDR, Pcie, Uart, I2c, Axi, IP verification, FPGA-based verification, APB, Uvm, C-based tests, systemverilog
Skills:
C, Python, AI-assisted development tools, emulation or FPGA-based verification, Uvm, systemverilog
Skills:
Fpga, Perl, Python, RTL, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, low power verification methods, object-oriented design, formal verification methods, transaction level modeling, test plan development, emulation platforms
Skills:
Test Planning, Debugging, Automation, Scripting, Validation
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