Pcie, System Verilog, Python, Systemc, Hybrid test benches, MDV, DV signoffs, SV, Uvm, UCIe, Axi, CDV

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

test environments , SystemVerilog Assertions (SVA, Gate-Level Simulation (GLS, Test Cases, Uvm, formal verification, Coverage measures, Constrained-random verification environments, systemverilog, Low power debug, Verification methodologies, Formal tools, Verification test benches

C, Perl, Python, Low power verification methods, FPGA emulator software environments, Emulation platforms, Uvm, systemverilog, Industry standard I/O interfaces, AMBA bus protocols, RTL development environments, Baremetal processor environments, Formal verification methods, UPF based low power verification, Transaction level modeling

Tcl, Python, Perl, Shell, Debugging RTL verification issues, Assertions SVA, Functional Verification, UVM methodology, systemverilog, Coverage-driven verification

simvision , python, Cadence simulation tools, Uvm, Xcelium, netlist simulation

code coverage , Nvme, Pcie, Ethernet, System Verilog, DDR, Uvm, Axi, APB, CXL, Industry-standard simulation and debug tools, UCIe, AHB, BFMs, Scoreboards, Checkers, Monitors, Functional coverage, Assertions

cache coherency , Uvm, DMA engines, ARM-based SoCs, memory systems, systemverilog, Transaction-level verification, CHI, Ace, AXI NoC architectures

code coverage , Cpu, Usb, Oops, Verilog, Arm, Networking, Ethernet, Pcie, DDR, AHB, spyglass, LINT, SV, Graphics, SoC Verification, cdc, AMBA, RTL Coding, VHDL, C tests, SV METH, Axi