Senior Design Verification Engineer
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We are hiring experienced ASIC Verification Engineers with strong hands‑on expertise in SystemVerilog, UVM, and IP/SOC verification. The role involves leading a small team, defining testbench architecture, developing UVM environments, and driving coverage closure. Experience with debug tools (IUS/VCS/Questa/Verdi), scripting (Python/Perl/Shell), and protocols like AXI, PCIe, DDR, USB, CXL, Ethernet, etc., is highly preferred. Knowledge of CPU-based verification, NoC, low‑power/GLS is a plus. Strong ownership and communication skills are essential.
Experience: 6+ years
Location: Hyderabad/Bangalore/Noida/Ahmedabad/Pune/Chennai
Job ID: 152470151
Skills:
JIRA, Perl, Python, checkers, Cadence SKILL, Uvm, Assertions, systemverilog, automatic reporting, AMBA bus protocol, Axi, vManager, random-constraint tests, cover-groups, monitors, AHB
Skills:
scoreboarding, memory controller architecture, AXI protocol, assertions SVA, Uvm, DDR protocol JEDEC specifications, functional coverage, GLS, systemverilog
Skills:
Usb, C, Debugging, Object Oriented Programming, Writing Test Cases, DDR, Ethernet, Perl, Pcie, Tcl, Function coverage, Coverage driven verification, IP Subsystem SOC ASIC Verification, Axi, Code coverage analysis, Test bench development, CXL, Simulation, Eth
Skills:
Uart, python, Debugging, SV, test cases coding, Uvm, Test bench development, IJTAG, APB, Code and Functional coverage analysis, Axi, BUS Protocols
Skills:
Nvme, Usb, Shell, Tcl, Verilog, System Verilog, Ethernet, Python, Pcie, Perl, DDR, UPF Low Power Verification, System Verilog Assertions, Uvm, Linux development environments, CHI, formal verification, CXL, Axi, NLP Testbench Verification, ASIC design flows
