Senior Design Verification Engineer
Senior Design Verification Engineer
ALTEN Calsoft LabsThis job is no longer accepting applications
Job Description
Senior Design Verification Engineer
- Looking for Verification engineer who is going to work on testbench development, test cases / assertions / functional coverage coding, debugging.
- Should be an enthusiastic and a quick learner of the verification flow.
Job Description:
- SV / UVM Test bench development and test cases coding
- Code and Functional coverage analysis and closure
- Work with team for verification closure
- Experience with python or any other scripting language is a plus
- Bus protocols AXI / APB / UART/ IJTAG protocol working knowledge is an advantage.
Experience: 4 to 6 Years
Location: Hyderabad
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Key Skills
About Company
Skills:
Noc, Usb, Vcs, DDR, Shell, Perl, Pcie, Ethernet, Python, Verdi, IUS, UVM environments, SystemVerilog UVM, GLS, coverage closure, debug tools, testbench architecture, Axi, IP SOC verification, Questa, CXL, CPU-based verification
Skills:
Usb, C, C++, Debugging, Test Plan, Object Oriented Programming, Writing Test Cases, Oop, DDR, Ethernet, Pcie, Perl, Tcl, Function coverage, Coverage driven verification, Uvm, IP Subsystem SOC ASIC Verification, Axi, Code coverage analysis, CXL, Test bench development, Simulation, System-Verilog
Skills:
C DPI Development, Hardware-Software Integration, Debugging Expertise, Scripting and Automation, Verification Planning, Uvm, systemverilog, SoC Verification, Coverage-Driven Verification
Skills:
Vcs, System Verilog, Verdi, DVE, Xcelium, Questa, Uvm, SVA assertions
Skills:
Usb, Nvme, DDR, Shell, Perl, Pcie, Verilog, Ethernet, Python, System Verilog, Tcl, UPF Low Power Verification, CHI, Linux development environments, Uvm, formal verification, ASIC design flows, Axi, CXL, NLP Testbench Verification, System Verilog Assertions