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Senior Design Verification Engineer
Job Description:
Experience: 4 to 6 Years
Location: Hyderabad
Job ID: 144789425
Skills:
Assembly Language, C, Ovm, PERL, Verilog, Shell script, System Verilog, Systemc, System Verilog PLI, Uvm, Emulation, Functional Verification, DPI interface, SoC Verification
Skills:
Perl, Verilog, Python, Tcl, VHDL, Uvm, systemverilog
Skills:
Nvme, Usb, Shell, Tcl, Verilog, System Verilog, Ethernet, Python, Pcie, Perl, DDR, UPF Low Power Verification, System Verilog Assertions, Uvm, Linux development environments, CHI, formal verification, CXL, Axi, NLP Testbench Verification, ASIC design flows
Skills:
rtl verification , Verilog simulations, Sram, AI-assisted tools, Timing Analysis, DRAM, UVM Test Bench, SystemVerilog PLI coding
Skills:
arm architecture , C, Usb, DDR, Pcie, Ethernet, SoC DV execution, hardware emulation support, TLMs in SystemC, Uvm, assertion-based formal verification tools, HBM
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