JIRA, Perl, Python, checkers, Cadence SKILL, Uvm, Assertions, systemverilog, automatic reporting, AMBA bus protocol, Axi, vManager, random-constraint tests, cover-groups, monitors, AHB

scoreboarding, memory controller architecture, AXI protocol, assertions SVA, Uvm, DDR protocol JEDEC specifications, functional coverage, GLS, systemverilog

Usb, C, Debugging, Object Oriented Programming, Writing Test Cases, DDR, Ethernet, Perl, Pcie, Tcl, Function coverage, Coverage driven verification, IP Subsystem SOC ASIC Verification, Axi, Code coverage analysis, Test bench development, CXL, Simulation, Eth

Uart, python, Debugging, SV, test cases coding, Uvm, Test bench development, IJTAG, APB, Code and Functional coverage analysis, Axi, BUS Protocols

Nvme, Usb, Shell, Tcl, Verilog, System Verilog, Ethernet, Python, Pcie, Perl, DDR, UPF Low Power Verification, System Verilog Assertions, Uvm, Linux development environments, CHI, formal verification, CXL, Axi, NLP Testbench Verification, ASIC design flows

arm architecture , C, Ethernet, Pcie, Usb, DDR, HBM, Uvm, SoC DV execution, assertion-based formal verification tools, TLMs in SystemC, hardware emulation support

System Verilog, Coverage models, DV methodology, Testbench design, Uvm

Jtag, System Verilog, Python, Pcie, Perl, UVM methodology, High speed USB, UltraSoC, RISC Debug Architectures, Design for Debug, Tessent Embedded Analytics

rtl verification , SystemVerilog PLI coding, Verilog simulations, Sram, AI-assisted tools, Timing Analysis, DRAM, UVM Test Bench