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Senior Design Verification Engineer:
Exp : 5–10 years experience
Location: Hyderabad
You will be responsible for verifying DDR4/5 memory controllers and AXI input interfaces for IP-level designs, ensuring full protocol compliance, error handling, data integrity and performance computation for high-speed DDR interfaces.
Education/Experience
Technical Skills
Key Responsibilities
Soft Skills
Job ID: 151583457
Skills:
Nvme, Usb, Shell, Tcl, Verilog, System Verilog, Ethernet, Python, Pcie, Perl, DDR, UPF Low Power Verification, System Verilog Assertions, Uvm, Linux development environments, CHI, formal verification, CXL, Axi, NLP Testbench Verification, ASIC design flows
Skills:
Makefile, Octave, MATLAB, Digital Signal Processing, Scripting Languages, Perl, Python, functional code coverage analysis, UVM-based testbench infrastructure, HW emulation, FPGA prototyping, formal verification, functional cover point development, Power aware simulations, gate level simulations, APB protocol, IP and SoC level verification, assertion development
Skills:
C, Perl, Python, System Verilog, formal verification tools, Microarchitecture, SOC integration, Uvm
Skills:
arm architecture , C, Ethernet, Pcie, Usb, DDR, HBM, Uvm, SoC DV execution, assertion-based formal verification tools, TLMs in SystemC, hardware emulation support
Skills:
System Verilog, Coverage models, DV methodology, Testbench design, Uvm