Senior Design Verification Engineer

We are a Singapore based Talent Transformation consulting firm, assisting our MNC client to set up their GCCs ( Global Capability Center) in Bangalore.

Qualification (s) BE/ BTech/ MTech/MS/ PhD

Domain - Electronics, Electrical, Computer Engineering or Computer Science Engineering

Experience 7+ years+

We are looking for a highly skilled and experienced Design Verification Engineer to join our team. This role is ideal for someone who brings deep technical expertise in verification along with a strong grasp of industry protocols and low-power design techniques. You'll work on advanced IP and SoC subsystems involving both RISC-V and ARM-based architecture, and collaborate closely with our architecture, design, and validation teams.

What You'll Do:

Own and drive the full verification cycle for IP blocks and subsystems

Create detailed verification plans, identify test items, and track coverage

Build UVM-based test benches from scratch, including drivers, monitors, and scoreboards

Perform low power verification using both UPF and Native Low Power (NLP) methods

Develop and run UVM-based test environments for Ethernet and other protocol interfaces

Integrate and work with third-party Verification IPs (VIPs)

Write and debug assertions and functional coverage models

Collaborate with design and architecture teams to close verification cycles efficiently

Support silicon bring-up and post-silicon debug when required

Mentor junior team members on verification techniques and best practices

Key Skills We Are Looking For:

UPF / Low Power Verification (UVM expert)

Strong understanding of low-power concepts in ASIC design (UPF/NLP) from a verification perspective

UVM with Ethernet protocol expertise

NLP Testbench Verification with Native Low Power (UVM expert)

Strong command over System Verilog, Verilog, and UVM methodology

Solid understanding of ASIC design flows and power-aware design concepts

Experience with protocols like PCIe, AXI, CHI, Ethernet, USB, NVMe, DDR, and CXL

Good working knowledge of System Verilog Assertions (SVA) and formal verification techniques

Hands-on experience with scripting (Python, Perl, Shell, TCL)

Comfortable working in Linux development environments

Excellent debugging, problem-solving, and analytical thinking

Strong communication and collaboration skills

Qualifications:

Bachelor's degree in Electrical Engineering, Electronics and Communications Engineering, Computer Engineering, Computer Science, or related fields

Fluent in both written and spoken English

Excellent collaborative skills

Highly motivated and self-driven individual

Strong coding and object-oriented programming skills

Excellent debugging, problem solving, and analytical skills

Knowledgeable in digital design

Minimum 7 years of industry experience in Design Verification roles.

A track record of successfully verifying complex IP blocks or subsystems from spec to silicon.