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Job Location: Hyderabad
Employment Type: Fulltime
Experience: 4 to 6 years
Accountable for innovative DFT implementation(Scan, MBIST, LBIST & Boundary Scan) at the RTL and Gate level for a given SOC at Hard macro and chip top level.
- Generate and validate ATPG patterns using simulations.
- Shall Validate the DFT implementation using RTL and Gate level simulation.
- Work with Multi-functional Teams on STA, Synthesis, LEC, CLP, verification & Validation.
- Must have experience with Siemens, Synopsys and/or Cadence Cad tools.
- Shall have experience in coding with Verilog, VHDL, C/C++, TCL, Perl and or Python
HighPoints Technologies India Private Limited
Job ID: 149302553
Skills:
DFT Design, MBIST, Scan Chains, Scan Compression, TAP, ATPG
Skills:
DFT planning, Cadence DFT toolchains, DFT architecture, RTL Verilog, scripting TCL, Scan, MBIST, quality metrics, Synopsys
Skills:
Test Methodology, DFT Architecture, Scan Insertion, Fault Simulation, DFT Tools, Debugging Skills, Rtl Design, Synthesis Tools, Timing Analysis, Tape-out Process
Skills:
test mode timing constraints definition, Genus Synopsys, DFT concepts, Scan Insertion, Transition delay test coverage analysis, TetraMax, simulating test vectors, ATPG coverage analysis, equivalence check, Cadence Encounter Test, DFTMax, ASIC DFT, timing fixes, DFT DRC rules
Skills:
PERL, Python, Tcl, Sta, LINT, Synthesis, cdc, RDC tools, DFT tools, Front-end Design, DFT methodologies
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