Senior DFT Engineer

Role Summary

We are looking for a highly experienced DFT Architect to define and drive end-to-end DFT architecture and flow methodology for next-generation silicon design programs. This role is focused on architectural ownership, methodology definition, and automation, rather than day-to-day vector execution.

The candidate will play a critical role during the early phase of flow creation, working cross-functionally with design methodology, RTL, PD, and automation teams to enable faster and more efficient design cycles.

Required Qualifications:

• 8+ years (preferably 10+ years) of hands-on DFT experience
• Proven experience defining DFT architecture, not just executing DFT insertion
• Background at end-to-end silicon companies

Strong understanding of:

• Scan, MBIST, DFT planning and quality metrics
• RTL (Verilog) – ability to write or review logic as needed
• Experience with Cadence DFT toolchains preferred
• (Synopsys experience acceptable

Desired Skills:

• Strong EDA flow and methodology mindset
• Experience automating constraints and flows from high-level specs
• Familiarity with scripting (TCL, Perl, Python) is a plus
• Ability to work independently with minimal supervision
• Excellent cross-functional collaboration skills
• Comfortable working in a global environment (IST hours with Japan overlap)

Role Type & Location

• Location: India (Hyderabad preferred; Bangalore remote acceptable)
• Work Hours: IST
• Travel: Occasional travel to Hyderabad may be required