DFT Design, MBIST, Scan Chains, Scan Compression, TAP, ATPG

DFT planning, Cadence DFT toolchains, DFT architecture, RTL Verilog, scripting TCL, Scan, MBIST, quality metrics, Synopsys

Test Methodology, DFT Architecture, Scan Insertion, Fault Simulation, DFT Tools, Debugging Skills, Rtl Design, Synthesis Tools, Timing Analysis, Tape-out Process

test mode timing constraints definition, Genus Synopsys, DFT concepts, Scan Insertion, Transition delay test coverage analysis, TetraMax, simulating test vectors, ATPG coverage analysis, equivalence check, Cadence Encounter Test, DFTMax, ASIC DFT, timing fixes, DFT DRC rules

PERL, Python, Tcl, Sta, LINT, Synthesis, cdc, RDC tools, DFT tools, Front-end Design, DFT methodologies

PERL, Python, Tcl, LINT, Sta, Synthesis, cdc, DFT tools, RDC tools, Front-end Design, DFT methodologies

PERL, Python, Tcl, Sta, Synthesis, DFT tools, RDC tools, Front-end Design, DFT methodologies

Unix, Jtag, Linux Os, Verilog, Scripting Languages, Ruby, Python, Perl, Tcl, IO-PHY loopback testing, EDA simulation tools, fuse, UVM verification methodologies, Scan, Verdi, SV, DFT feature verification, MBIST, systemverilog, file version control, debug tools, Synopsys VCS, Cadence NCSIM, SVA

logic bist , C, Jtag, Perl, Verilog, Python, Tcl, Scan and Memory Diagnosis, PDT, Memory BIST and Repair implementation, IEEE1687, ATPG Fault models, BSCAN, Scan Codec insertion, IEEE1149.1, SDF annotated gate level verification, VHDL, Fault Simulation, SDD, ATPG, TDF, SAF

PERL, Python, Tcl, LINT, Sta, Synthesis, cdc, DFT tools, RDC tools, Front-end Design, DFT methodologies