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We are seeking an experienced DFT Engineer to join our team in India. The ideal candidate will have a strong background in Design for Test methodologies and will be responsible for implementing DFT strategies for our integrated circuit designs. This role involves collaboration with various engineering teams to ensure that our products are designed for optimal testability, which is critical for achieving high-quality outcomes.
Job ID: 147154631
Skills:
Fpga, DDR, High Speed SERDES, Test Development, RTL Custom Logic design, MBIST, Mixed Signal IPs, Verification, ATE test, P R STA Integration, Pll, tool development methodology, Synthesis, DFT EDA tools, multi-processors SOC, characterization, SOC Scan
Skills:
logic bist , Jtag, PERL, Shell script, Python, E-fuse, Pattern Retargeting, BSDL, Pattern simulation, Post Silicon debug analysis, DFT architectures, IDDQ, Chip level DFT, Fault Models, ATPG Pattern generation, scan chain insertion and verification, SDC constructs for DFT modes, Digital design concepts, pattern generation for Memories, MBIST, Scan Compression Techniques, JTAG IJTAG, ATPG coverage analysis, Transition faults, stuck at, scan patterns and coverage statistics
Skills:
boundary scan , Vcs, Perl, Python, Tcl, Scan Insertion, Post-silicon validation, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, Tessent tool sets, TestMax
Skills:
Vcs, ATE patterns, Scan Insertion, Tessent, JTAG protocols, ATPG, Gate level simulation, Post-silicon validation, P1687, TestMax, TetraMax
Skills:
DFT features, DFT signoff, IO BIST, test access mechanisms, ATPG, Scan Insertion, memory BIST, test coverage driven ATPG closure
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