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DFT Engineer
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DFT Engineer
Proxelera Private LimitedThis job is no longer accepting applications
Job Description
Key Responsibilities:
- Implement and verify DFT logic including MBIST, scan chains, scan compression, TAP, iJTAG, and eFuse.
- Perform scan insertion, ATPG pattern generation, and coverage analysis.
- Execute MBIST insertion, simulation, and debug at RTL and gate levels.
- Collaborate with silicon and test engineering teams to create test plans and generate test patterns.
- Participate in post-silicon bring-up, diagnostics, and characterization activities.
- Work with EDA and IP vendors to adopt advanced DFT/DFD/DFY methodologies.
- Integrate DFT/BIST flows into synthesis and ensure timing closure across all stages.
- Utilize Verilog HDL, simulation, and waveform debugging tools for design verification.
- Apply strong understanding of clock domain crossings and the impact of DFT on synthesis and physical design.
- Hands-on experience with Mentor DFT and Synopsys simulation tools is essential.
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About Company
Proxelera is your premier outsourced product development partner (OPD), specializing in Semiconductors, Systems, and Bespoke Hardware. Proxelera combines process rigour with advanced technical expertise to deliver transformative solutions while fostering industry-academia collaboration and VLSI talent development.
Skills:
MBIST, ATPG, Dft, Scan Insertion, Siemens Tessent, DFT Simulation
Early Applicant
Skills:
boundary scan , bist , Jtag, Debugging, physical design constraints, Sta, verification flows, ATE test pattern generation, compression techniques, MBIST, Analytical Skills, TetraMax, Synopsys DFT Compiler, DFT tools, Tessent, silicon bring-up, Scan ATPG, LBIST, RTL design synthesis
Skills:
Sed, Jtag, Awk, Tcl, Dft, Tessent, ATPG, Scan, MBIST, LBIST, Spyglass-DFT
Skills:
bist , boundary scan , Jtag, test compression, ATPG, EDA Tools, Scan Insertion, DFT methodologies, Logic Memory, Synopsys TestMAX, Mentor Tessent
Skills:
MBIST Insertion Verification, ATPG Coverage Analysis Debug, Scan Insertion Compression, Boundary Scan Verification, Mentor Cadence Synopsys Tools