TSMC 7nm, IR drop, Analog RF layout techniques, ESD verification, LOD, FinFET nodes, circuit design analysis, WPE, Latch-up, Analog Layout, ERC checks, TSMC 16nm, Esd, EM issues, high-complexity RF designs, Custom RF, Samsung 8nm

shielding , matching , Parasitics, PEX, Analog circuit basics, Layout techniques, LVS, EM IR, Layout-dependent effects, Deep-submicron CMOS technologies, Analog Mixed-Signal IC Layout, DRC, Analog Custom Layout, Cadence Virtuoso

guard rings, PEX, Reliability, dummy structures, symmetry shielding, LVS, advanced-node custom layout, matching performance, ERC, DRC, matching-critical layouts, common-centroid interdigitation, Cadence Virtuoso, 2nm 3nm 5nm FinFET

Analog layout design, Cadence Tools, FinFet experience, Debugging DRC, LVS, RF layout, Analog layout concepts for deep sub-micron processes, Floorplan, TSMC processes, Top-level integration, and antenna errors

post-layout simulation, analog circuit theory, DRC, Mentor Graphics, analog and mixed-signal AMS design, LVS, Synopsys, Cadence Virtuoso, Analog Layout, semiconductor device physics

Layout verification tools, Design rule checking processes, Analog Layout Design, Parasitic Extraction

matching , Electromigration (EM), Routing, Shielding coupling crosstalk, DC-DC Converter Layout Development, Floorplan optimization, Cadence Virtuoso Editor, IR-drop, Active passive parasitic devices, Analog Layout Design, ESD Latch-up, Calibre, Mixed-Signal Layout Design, BCD Technology, Effort area estimation, Physical verification sign-off, DRC, Layout checks, Analog Layout fundamentals, LVS

Synopsys IC Validator, 7nm FinFET technology, multi-patterning awareness, Cadence Virtuoso Layout Suite, Cadence Pegasus, high-speed analog and mixed-signal layout design, Calibre DRC LVS PEX, device matching, LVS, extracted netlists, Custom Compiler, ERC checks, DRC, parasitic optimization, reliability rules