Analog Layout Engineer
Analog Layout Engineer
Prodapt4-6 Years
- Posted 12 hours ago
- Be among the first 10 applicants
Job Description
Job Description:
- 4 – 6+ years of hands-on block-level Analog Layout (Custom & RF) experience.
- Experience should be on FinFET nodes, preferably 3–7nm.
- Experience in Samsung 8nm, TSMC 7nm, and TSMC 16nm; Samsung 8nm is an advantage.
- Strong knowledge of Analog/RF layout techniques and current industry methodologies.
- Experience in circuit design analysis, layouts, LVS/DRC/ERC checks, and ESD verification for high-complexity RF designs.
- Candidates should have successfully completed a couple of full project cycles from floor plan to tape-out.
- Good knowledge of ESD, LOD, WPE, Latch-up, IR drop, and EM issues and fixes.
More Info
Key Skills
TSMC 7nm
IR drop
Analog RF layout techniques
ESD verification
LOD
FinFET nodes
circuit design analysis
WPE
Latch-up
ERC checks
TSMC 16nm
EM issues
high-complexity RF designs
Custom RF
Samsung 8nm
About Company
Skills:
shielding , matching , Parasitics, PEX, Analog circuit basics, Layout techniques, LVS, EM IR, Layout-dependent effects, Deep-submicron CMOS technologies, Analog Mixed-Signal IC Layout, DRC, Analog Custom Layout, Cadence Virtuoso
Skills:
Analog layout design, Cadence Tools, FinFet experience, Debugging DRC, LVS, RF layout, Analog layout concepts for deep sub-micron processes, Floorplan, TSMC processes, Top-level integration, and antenna errors
Skills:
post-layout simulation, analog circuit theory, DRC, Mentor Graphics, analog and mixed-signal AMS design, LVS, Synopsys, Cadence Virtuoso, Analog Layout, semiconductor device physics
Skills:
Analog Layout, Design for manufacturability and testing requirements, Analog circuit design principles, Parasitic extraction and mitigation techniques
Skills:
matching , Electromigration (EM), Routing, Shielding coupling crosstalk, DC-DC Converter Layout Development, Floorplan optimization, Cadence Virtuoso Editor, IR-drop, Active passive parasitic devices, Analog Layout Design, ESD Latch-up, Calibre, Mixed-Signal Layout Design, BCD Technology, Effort area estimation, Physical verification sign-off, DRC, Layout checks, Analog Layout fundamentals, LVS