Analog Layout Engineer
Analog Layout Engineer
Broadcom8-10 Years
- Posted 22 hours ago
- Be among the first 10 applicants
Job Description
Job Description:
- Analog layout designer providing onsite support for advanced nodes, working with global layout and design team.
- Candidate should work independently on block level and IP level Analog layout design, coordinating with the circuit designer & the layout team
- Candidate should have minimum 8+ years of hands-on experience in Analog or RF layout.
- Should have worked on floorplan and layout for analog modules like SerDes, ADC/DAC, PLL, etc.
- Should have worked on and top-level integration
- Should have a good understanding of analog layout concepts for deep sub-micron processes and knowledge of fabrication process, preference will be given to FinFet experience candidates.
- Should have a good understanding of ESD, latch-up, EM, and strong skills debugging DRC, LVS, and antenna errors.
- Job Complexity: Works on complex issues where analysis of situations or data requires an in-depth evaluation of variable factors. Exercises judgment in selecting methods, techniques and evaluation criteria for obtaining results. Networks with key contacts outside own area of expertise.
- Supervision: Determines methods and procedures on new assignments and may coordinate activities of other personnel (Team Lead).
- Experience with Cadence tools and TSMC processes are preferred
More Info
Job Type:
Industry:
Function:
Employment Type:
Key Skills
Analog layout design
FinFet experience
Debugging DRC
RF layout
Analog layout concepts for deep sub-micron processes
TSMC processes
Top-level integration
and antenna errors
About Company
Skills:
guard rings, PEX, Reliability, dummy structures, symmetry shielding, LVS, advanced-node custom layout, matching performance, ERC, DRC, matching-critical layouts, common-centroid interdigitation, Cadence Virtuoso, 2nm 3nm 5nm FinFET
Skills:
Analog Layout, Design for manufacturability and testing requirements, Analog circuit design principles, Parasitic extraction and mitigation techniques
Skills:
matching , Electromigration (EM), Routing, Shielding coupling crosstalk, DC-DC Converter Layout Development, Floorplan optimization, Cadence Virtuoso Editor, IR-drop, Active passive parasitic devices, Analog Layout Design, ESD Latch-up, Calibre, Mixed-Signal Layout Design, BCD Technology, Effort area estimation, Physical verification sign-off, DRC, Layout checks, Analog Layout fundamentals, LVS
Skills:
ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques
Skills:
matching , Bandgap Oscillators, xACT, LVS, EM, IR drop, Cadence Tools, parasitic effects, MXL, reference circuits, LVS DRC PEX EMIR verification flows, Quantus, GXL, EXL, Xl, Voltus, Calibre DRC, LDOs, StarRC