Analog Layout Engineer
Analog Layout Engineer
leadsoc technologies pvt ltd4-10 Years
- Posted 19 hours ago
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Job Description
Analog Layout Engineer
Location: Bengaluru
Experience: 4–10 Years
Role Overview
We are looking for a hands-on Analog Layout Engineer with strong experience in advanced-node custom layout for analog/mixed-signal IPs. The role involves ownership of layout implementation, optimization, physical verification, and signoff for next-generation semiconductor designs.
Key Responsibilities
- Execute custom analog/mixed-signal layout from schematic to signoff.
- Work on advanced nodes: 2nm, 3nm, 5nm, FinFET.
- Implement matching-critical layouts using common-centroid, interdigitation, symmetry, shielding, guard rings, and dummy structures.
- Optimize area, parasitics, matching, performance, and reliability.
- Drive DRC/LVS/ERC/PEX closure and resolve physical verification issues.
- Collaborate closely with Circuit Design, Physical Verification, CAD, and Technology teams.
- Support post-layout extraction and simulation and address layout-dependent performance issues.
Core Technical Requirements
- 4–10 years of hands-on Analog/Custom Layout experience.
- Strong expertise in advanced-node layout and FinFET technologies.
- Proficiency in Cadence Virtuoso or equivalent custom layout tools.
- Strong understanding of DRC, LVS, ERC, PEX, parasitic extraction, and signoff.
- Experience with complex analog/mixed-signal blocks.
- Strong understanding of device matching, layout-dependent effects, and advanced-node design rules.
More Info
Job Type:
Industry:
Function:
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Key Skills
guard rings
PEX
dummy structures
symmetry shielding
advanced-node custom layout
matching performance
DRC
matching-critical layouts
common-centroid interdigitation
2nm 3nm 5nm FinFET
About Company
Skills:
Analog layout design, Cadence Tools, FinFet experience, Debugging DRC, LVS, RF layout, Analog layout concepts for deep sub-micron processes, Floorplan, TSMC processes, Top-level integration, and antenna errors
Skills:
post-layout simulation, analog circuit theory, DRC, Mentor Graphics, analog and mixed-signal AMS design, LVS, Synopsys, Cadence Virtuoso, Analog Layout, semiconductor device physics
Skills:
matching , Electromigration (EM), Routing, Shielding coupling crosstalk, DC-DC Converter Layout Development, Floorplan optimization, Cadence Virtuoso Editor, IR-drop, Active passive parasitic devices, Analog Layout Design, ESD Latch-up, Calibre, Mixed-Signal Layout Design, BCD Technology, Effort area estimation, Physical verification sign-off, DRC, Layout checks, Analog Layout fundamentals, LVS
Skills:
reliability driven layout practices, Calibre, analog mixed-signal IC layout, PEX, DRC, parasitic-aware layout, antenna rules, post-layout simulation correlation, LVS, Cadence Virtuoso
Skills:
FinFET GAA layout concepts, Cadence Virtuoso Custom Layout, Calibre PVS, advanced-node analog custom layout, PEX, parasitic optimization, physical verification flows, post-layout simulation correlation, matching shielding guard rings isolation