shielding , matching , Parasitics, PEX, Analog circuit basics, Layout techniques, LVS, EM IR, Layout-dependent effects, Deep-submicron CMOS technologies, Analog Mixed-Signal IC Layout, DRC, Analog Custom Layout, Cadence Virtuoso

VXL, TSMC 16nm 5nm 3nm, EM, LVS, Dfm, Analog Mixed-Signal Custom Layout, VLE, DRC, Intel Samsung GF, Antenna, IR verification flows, Cadence Virtuoso, Mentor Graphics Calibre DRC

caliber , Verification Tools, Layout Design, Cadence Virtuoso

Shell, PERL, Tcl, Assura, Skill, Memory layout design, Cadence Virtuoso

scripting expertise, Cadence LVS, Calibre physical verification flow, layout XL, EXL, Cadence Virtuoso, layout design and verification tools, GXL

post-layout simulation, analog circuit theory, DRC, Mentor Graphics, analog and mixed-signal AMS design, LVS, Synopsys, Cadence Virtuoso, Analog Layout, semiconductor device physics

guard rings, PEX, Reliability, dummy structures, symmetry shielding, LVS, advanced-node custom layout, matching performance, ERC, DRC, matching-critical layouts, common-centroid interdigitation, Cadence Virtuoso, 2nm 3nm 5nm FinFET

matching , Routing, Parasitics, Memory Array Layout, Sram, LVS, NVM, Physical Verification, Calibre, floorplanning, Layout Optimization, Custom Layout, Memory Layout, Cadence Virtuoso, Placement, ERC, Hierarchical Layout, DRC, FinFET Technology, PPA Optimization, Memory Compiler, Rom