C
Memory Layout Engineer
C
Memory Layout Engineer
Capgemini3-7 Years
- Posted 19 hours ago
- Be among the first 10 applicants
Job Description
Job Location: Bangalore
This role is for a Memory Layout Engineer with 3-7 years of experience to design and develop memory blocks for integrated circuits (ICs). You will be responsible for creating efficient memory layouts that meet performance, power, and area constraints.
Responsibilities:
- Design memory layouts for various building blocks including:
- Bit cell array
- Row decoder
- Column decoder
- Sense amplifiers
- Input/Output (I/O) blocks
- Integrate top-level memory blocks
- Perform physical verification using tools like Design Rule Check (DRC) and Layout Versus Schematic (LVS)
- Ensure layouts meet Design for Manufacturability (DFM) and Design for Yield (DFY) requirements
- Analyze layouts for potential power and signal integrity issues
- May involve scripting using languages like PERL, Shell, TCL, or Skill
Qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
- 3-5 years of experience in memory layout design
- Proven experience with memory layout tools like Cadence Virtuoso and Assura
- Understanding of memory compiler architectures and sub-blocks
- Experience with low-power, high-performance, and high-density SRAM memory design (experience with different technology nodes is a plus)
- Knowledge of Design for Manufacturability (DFM) and Design for Yield (DFY) concepts
- Strong analytical and problem-solving skills
- Excellent communication and teamwork abilities
Preferred Skills:
- Experience with custom and compiler-based memory layout
- Experience with FinFET process technologies
- Experience with memory verification methodologies
Requirements added by the job poster
• 3+ years of work experience with SRAM
• 3+ years of work experience with Layout Design
More Info
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Key Skills
About Company
Skills:
shielding , routing, guard rings, Custom Layout, LVS, Memory Layout, Calibre, CMOS devices matching techniques, advanced technology nodes, common-centroid layout, ERC, DRC, Cadence Virtuoso
Skills:
matching , Routing, Parasitics, Memory Array Layout, Sram, LVS, NVM, Physical Verification, Calibre, floorplanning, Layout Optimization, Custom Layout, Memory Layout, Cadence Virtuoso, Placement, ERC, Hierarchical Layout, DRC, FinFET Technology, PPA Optimization, Memory Compiler, Rom
Skills:
parasitic effects, PEX, Cadence Virtuoso Custom Layout, 5nm FinFET, FinFET layout techniques, matching symmetry, LVS, memory custom layout, design-rule requirements, shielding guard rings, SRAM bitcell memory arrays, layout optimization, ERC, DRC, parasitic optimization, sensitive-net routing, Calibre PVS, advanced-node tapeout
Skills:
Layout fundamentals, Memory design basics
Memory Layout Engineer | Bangalore | 5-10 Years Experience | Immediate to 15 day Notice period onlyheadway tek inc
Skills:
physical closure, Synopsys, top-level memory integration, decoders, memory compiler IPs, bit-cell arrays, Sram, LVS, collaboration with circuit design, layout experience, sense amplifiers, power performance, yield manufacturability, verification PDK methodology teams, Cadence, optimize layouts for area, IR EM challenges, density verification, FinFET design rules, DFM guidelines, memory periphery, DRAM, DRC, layout and physical verification tools