Search by job, company or skills

Showing 9 jobs

Bengaluru, India

Skills:

Analog layout designCadence ToolsFinFet experienceDebugging DRCLVSRF layoutAnalog layout concepts for deep sub-micron processesFloorplanTSMC processesTop-level integrationand antenna errors

Early Applicant
Bengaluru, India

Skills:

post-layout simulationanalog circuit theoryDRCMentor Graphicsanalog and mixed-signal AMS designLVSSynopsysCadence VirtuosoAnalog Layoutsemiconductor device physics

Early Applicant
Bengaluru, India

Skills:

matching Electromigration (EM)RoutingShielding coupling crosstalkDC-DC Converter Layout DevelopmentFloorplan optimizationCadence Virtuoso EditorIR-dropActive passive parasitic devicesAnalog Layout DesignESD Latch-upCalibreMixed-Signal Layout DesignBCD TechnologyEffort area estimationPhysical verification sign-offDRCLayout checksAnalog Layout fundamentalsLVS

Early Applicant
Bengaluru, India

Skills:

reliability driven layout practicesCalibreanalog mixed-signal IC layoutPEXDRCparasitic-aware layoutantenna rulespost-layout simulation correlationLVSCadence Virtuoso

Early Applicant
Bengaluru, India

Skills:

FinFET GAA layout conceptsCadence Virtuoso Custom LayoutCalibre PVSadvanced-node analog custom layoutPEXparasitic optimizationphysical verification flowspost-layout simulation correlationmatching shielding guard rings isolation

Early Applicant
Bengaluru, India

Skills:

ICValidatorSOILVSMentor GraphicsAnalog layout designTSMC PDKsCalibreMultiple layout design environmentsSynopsys IC CompilerTSMC 7nmCadence VirtuosoDRCParasitic ExtractionStatistical analysis toolsFinFETMixed-signal layoutsLow-power design techniques

Early Applicant
Bengaluru, India

Skills:

shielding ESD latch-up preventionAnalog Custom Layout DesignGuard ringsTI Texas Instruments project environmentCadence VirtuosoMatching symmetryLayout verification toolsCommon centroidAdvanced process nodes foundry rulesDRC LVS ERC EM IR checks

Early Applicant
Bengaluru, India

Skills:

matching Bandgap OscillatorsxACTLVSEMIR dropCadence Toolsparasitic effectsMXLreference circuitsLVS DRC PEX EMIR verification flowsQuantusGXLEXLXlVoltusCalibre DRCLDOsStarRC

Early Applicant
Bengaluru, India

Skills:

analog layout conceptsMentor CalibreCadence Virtuoso XLFinFET technologies

Early Applicant
Advertisement
Beware of Scammers

We don’t charge money for job offers