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Job ID: 137801121
Skills:
Calibre, Analog Layout, Cadence Virtuoso XL, Design for Manufacturability Principles, Signal Integrity Analysis, Power Distribution Techniques
Skills:
Shell, Perl, Cadence LVS, scripting knowledge in Skill, FinFet technology layout design, DRC limitations, Calibre physical verification flow, layout XL, debugging skills, layout design and verification tools, Cadence Virtuoso, GXL
Skills:
Synopsys StarRC, R3D, DRC, Mentor Graphics Calibre, LVS, Cadence Voltus, xACT, Cadence MXL
Skills:
ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques
Skills:
Cadence Tools, BCD process, Mentor Tools Calibre, Mixed Signal and Analog Layout, Dongbu PDK, layout of Analog blocks reference amplifier data converters
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