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Job ID: 150873229
Skills:
bandgap references , Common-centroid layout, ADC DAC-related circuits, Parasitic effects, Amplifiers, LVS, physical verification sign-off flows, ESD and latch-up considerations, TSMC process nodes, Differential Pairs, Analog Mixed-Signal Layout Design, Interdigitation, ERC, Current Mirrors, DRC, Cadence Virtuoso, Device matching techniques, LDOs
Skills:
post-layout simulation, DRC, Mentor Graphics, analog and mixed-signal AMS design, LVS, Synopsys, Cadence Virtuoso, Analog Layout
Skills:
matching , shielding , Tcl, Perl, Clock Routing, Resistance and capacitance reduction, EMIR simulations, Cadence Virtuoso, signal flow, High-Speed Analog Custom layout development, Mentor, Bias and Power routing
Skills:
Cadence Virtuoso, EMIR simulations, Custom layouts, Mentor
Skills:
analog layout concepts, Mentor Calibre, Cadence Virtuoso XL, FinFET technologies
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