Analog Layout Engineer
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Job Description
Job Title: Analog Layout Engineer
Experience: 5+ Years
Location: Bangalore
Job Description
We are looking for an experienced Analog Layout Engineer with 5+ years of experience in custom/analog layout design. Candidate should have strong hands-on experience in TI (Texas Instruments) project environment / TI-based project exposure, along with expertise in layout implementation, verification, and tapeout support for analog and mixed-signal blocks.
Key Responsibilities
Experience: 5+ Years
Location: Bangalore
Job Description
We are looking for an experienced Analog Layout Engineer with 5+ years of experience in custom/analog layout design. Candidate should have strong hands-on experience in TI (Texas Instruments) project environment / TI-based project exposure, along with expertise in layout implementation, verification, and tapeout support for analog and mixed-signal blocks.
Key Responsibilities
- Work on Analog / Custom Layout for blocks such as PLL, ADC, DAC, LDO, Bandgap, SRAM, IO, and other mixed-signal circuits
- Perform layout floorplanning, device matching, routing, shielding, and parasitic-aware layout design
- Ensure layout follows DRC, LVS, ERC, and EM/IR design rules and quality standards
- Collaborate with circuit designers, verification, and PV teams for layout closure
- Handle block-level and top-level layout integration
- Support tapeout activities and signoff closure
- Optimize layout for area, performance, reliability, and manufacturability
- 5+ years of experience in Analog / Custom Layout Design
- Hands-on experience in TI project / Texas Instruments project environment
- Strong knowledge of matching, symmetry, shielding, common centroid, guard rings, ESD, latch-up prevention
- Experience in DRC, LVS, ERC, EM/IR checks and fixing layout issues
- Good understanding of analog and mixed-signal design concepts
- Experience with Cadence Virtuoso and related layout verification tools
- Familiarity with advanced process nodes / foundry rules
More Info
Key Skills
ESD latch-up prevention
Layout verification tools
Analog Custom Layout Design
Advanced process nodes foundry rules
Common centroid
TI Texas Instruments project environment
DRC LVS ERC EM IR checks
Matching symmetry
Guard rings
About Company
Skills:
Debugging, Physical Verification Tools, PEX, FinFET, LVS, Layout Optimization, ERC, DRC, Post-layout Verification, Analog Custom Layout, High-performance Analog Mixed-Signal Blocks, Advanced Technology Nodes, Cadence Virtuoso
Skills:
Pvs, Python, Tcl, Methodology, FinFET nodes, Floorplan to Tape-out, Reliability Effects, Layout Techniques, Scripting in SKILL, Circuit Analysis, Verification, ESD Latch-Up, LDE Reliability, Assura, Calibre, Physical Verification, Collaboration, Project Cycles, Analog RF Layout, Power Routing, Cadence Virtuoso
Skills:
post-layout simulation, analog circuit theory, DRC, Mentor Graphics, analog and mixed-signal AMS design, LVS, Synopsys, Cadence Virtuoso, Analog Layout, semiconductor device physics
Skills:
Synopsys IC Validator, 7nm FinFET technology, multi-patterning awareness, Cadence Virtuoso Layout Suite, Cadence Pegasus, high-speed analog and mixed-signal layout design, Calibre DRC LVS PEX, device matching, LVS, extracted netlists, Custom Compiler, ERC checks, DRC, parasitic optimization, reliability rules
Skills:
layout verification , ICValidator, multiple layout design environments, FinFET, advanced packaging technologies, LVS, SOI, Calibre, mixed-signal layouts, Synopsys IC Compiler, high-speed layout techniques, statistical analysis tools, DRC, Parasitic Extraction, Mentor Graphics, TSMC PDKs, analog layout design, low-power design techniques, Cadence Virtuoso