Analog Layout Engineer

Analog Layout Engineer

Required Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 4+ years of experience in analog layout design with a focus on TSMC 7nm, 5nm, and 3nm process technologies.
• Proficiency with Cadence Virtuoso, Mentor Graphics, Synopsys IC Compiler, or equivalent analog layout tools.
• Hands-on experience with TSMC PDKs and process technologies for 7nm, 5nm, and 3nm nodes.
• Strong knowledge of analog circuit design principles, including transistor-level design, biasing, signal integrity, and noise analysis.
• Extensive experience with DRC, LVS, parasitic extraction, and layout verification using tools such as Calibre and ICValidator.
• In-depth knowledge of FinFET, SOI, and other advanced semiconductor process technologies at sub-7nm nodes.
• Ability to optimize analog layouts for PPA (performance, power, area).
• Experience with low-power design techniques in advanced process nodes.
• Familiarity with high-performance analog designs and layouts in 7nm, 5nm, and 3nm technologies.
• Strong problem-solving skills and ability to troubleshoot and resolve layout issues.

Preferred Qualifications:

• Experience with mixed-signal layouts (analog and digital) for full-chip designs.
• Familiarity with RF layout techniques for high-frequency analog circuits.
• Experience in working with multiple layout design environments (e.g., Virtuoso, IC Studio, Synopsys Custom Compiler).
• Knowledge of electromagnetic interference (EMI), signal integrity, and high-speed layout techniques in advanced nodes.
• Exposure to full-custom layout techniques for complex analog IC designs.
• Understanding of advanced packaging technologies and their impact on analog layout design.
• Experience with statistical analysis tools for yield and design optimization.

Location: Bangalore

Experience: 4 to 8 Years