MATLAB, Python, VHDL-AMS, Verilog-AMS, Mentor Graphics, Synopsys, Cadence Virtuoso

cadence spectre , simvision , Hdl, shell scripting, Perl, Python, Tcl, Xcelium, mixed-signal design verification, Cadence Mixed-Signal Design Environment tools, SV RNM verilogAMS, VIVA, Virtuoso ADE, Assembler, SV UVM

Synopsys VCS, Cadence Xcelium, EDA Tools, Verilog-AMS, SV-RNM, Uvm, Verilog-A, systemverilog, Spectre

System Verilog, Visual Studio Code, Uvm, Spectre, Cadence Xcelium-AMS, Hspice, Mixed-Signal verification, GitHub Copilot

automation, Scripting, SoCs, Real model creation, mixed signal verification fundamentals, PSL SV assertions development, model validation, VerilogA, SV Verilog, environment development, verification planning, Verilog-AMS, verification of Power management IPs, behavioral modelling of analog blocks

rtl verification , Debugging, AMS IP Verification, AMS IP Integration, SoC-Level Verification, Sub-System Verification, PDL Test Case Development, Gate-Level Simulation, Timing Simulation, Virtual Tester Simulation, Tessent DFT, DFT Pattern Generation, Pattern Simulation, Testbench Bring-Up

simvision , Cadence Xcelium, AMS SPICE, DMSO, verification planning, testcase creation, testbench development, Verisium, simulation debug, Cadence Virtuoso, Xps, Spectre UltraSim, analog mixed-signal simulation