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Analog Mixed Signal Verification
Description of Services:
Verification task is to verify power management unit with several LDOs and DCDC converter, also including SAR-ADC for monitoring purposes.
Implement top level sequences in directed testcases, together with checks on digital and analog signals
Some randomization of testcases may be required
Quickly ramp-up on internal UVCs used in Infineon projects
As a plus, utilization of GitHub Copilot in Visual Studio Code for efficient sequence generation
Deliverables and Results:
Implement top level sequences in directed testcases, together with checks on digital and analog signals
Some randomizations of testcases may be required
TSMC relevant
yes
Requirements:
Mixed-Signal verification, with good knowledge in UVM and System Verilog
Good understanding of architecture description, and conversion to a verification plan
Education:
BTech/MTech in Electronics/Electrical Engineering
Professional Background & Experience:
Minimum of 4 years of experience in AMS verification
Prior Knowledge:
Tooling: Cadence Xcelium-AMS with spectre for analog parts and hspice measurement
Good to have: Github Copilot in Visual Studio Code
Job ID: 147210059
Skills:
Tcl Scripting, Unix Shell Scripting, Perl, Verilog, Python, System Verilog, Incisive, IMC, behavioral modelling, Uvm, Spectre, xCelium, vManager, VerilogAMS, mixed signal verification
Skills:
Mixed-Signal DV, AMS Verification, Analog Modeling, systemverilog, behavioral modeling, Chip Verification
Skills:
analog circuits , Unix Environment, DDR, shell scripting, Verilog, Python, Models, memory subsystems, digital design processes, simulation debugging, RTL, Uvm, top-level integration, systemverilog, Schematics, VerilogAMS
Skills:
Register modeling, coverage analysis, firmware interaction, regression management, SERDES, Uvm, systemverilog, PHY architectures
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