AMS verification engineer
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Analog Mixed Signal Verification
Description of Services:
Verification task is to verify power management unit with several LDOs and DCDC converter, also including SAR-ADC for monitoring purposes.
Implement top level sequences in directed testcases, together with checks on digital and analog signals
Some randomization of testcases may be required
Quickly ramp-up on internal UVCs used in Infineon projects
As a plus, utilization of GitHub Copilot in Visual Studio Code for efficient sequence generation
Deliverables and Results:
Implement top level sequences in directed testcases, together with checks on digital and analog signals
Some randomizations of testcases may be required
TSMC relevant
yes
Requirements:
Mixed-Signal verification, with good knowledge in UVM and System Verilog
Good understanding of architecture description, and conversion to a verification plan
Education:
BTech/MTech in Electronics/Electrical Engineering
Professional Background & Experience:
Minimum of 4 years of experience in AMS verification
Prior Knowledge:
Tooling: Cadence Xcelium-AMS with spectre for analog parts and hspice measurement
Good to have: Github Copilot in Visual Studio Code
Job ID: 147210059
Skills:
monte carlo , Python, Functional Coverage, power management, Analog Mixed-Signal, Uvm, Assertions, systemverilog, Pvt, Mixed-Signal Debug, Verification Automation, RNM, AMS Verification, Verilog-AMS, Spice, AMS Simulation, PMIC
Skills:
automation, Scripting, environment development, mixed signal verification fundamentals, Real model creation, verification planning, behavioral modelling of analog blocks, SoCs, model validation, verification of Power management IPs, PSL SV assertions development, Verilog-AMS, SV Verilog, VerilogA
Skills:
Perl, Shell Scripts, Python, Tcl, Synopsys XA VCS, Verilog-AMS, Spectre AMS Designer, SystemVerilog RNM Real Number Modeling, Cadence Virtuoso, SystemVerilog UVM
Skills:
Mentor, Uvm, firmware interaction, Synopsys, AMs, systemverilog, Cadence, Siemens, Calibration and link training flows, Register models, industry VIPs, Avery, SERDES
Skills:
Verilog, Uvm, testbench creation, code coverage analysis, DFI protocols, logic simulation, systemverilog, Verilog-A, score boarding, AMS simulations, RTL debugging
