AMS Verification Engineer
AMS Verification Engineer
ALTEN Calsoft Labs4-6 Years
- Posted 9 days ago
- Be among the first 10 applicants
Job Description
Job Opportunity: AMS Verification Engineer
Company: ACL Digital
Location: Bangalore
Experience Required: 4+ Years
Notice Period: 15–30 Days
Are you ready to accelerate your career in the semiconductor industry ACL Digital is hiring experienced Analog Mixed-Signal (AMS) Verification Engineers to work on high-impact projects with global technology leaders in Bangalore.
Key Responsibilities:
- Drive AMS verification strategies, including the development of complex testbenches and behavioral models.
- Work on mixed-signal co-simulations (AMS/DMS) and ensure functional and code coverage closure.
- Collaborate with design and architecture teams to resolve complex functional and performance issues.
- Contribute to verification planning, methodology definition, and execution at the block or SoC level.
Desired Qualifications:
- Experience: 4+ years of hands-on experience in Analog Mixed-Signal (AMS) or Digital Design Verification.
- Skills: Strong proficiency in SystemVerilog, UVM, and modeling languages (Verilog-AMS, Verilog-A, SV-RNM).
- Tooling: Familiarity with EDA tools such as Cadence Xcelium/Spectre, Synopsys VCS, or similar environments.
- Core Competency: Solid understanding of analog building blocks (e.g., PLLs, ADCs/DACs, PMIC).
What We Offer:
- Opportunity to work on next-generation silicon designs.
- Collaborative environment with top-tier global semiconductor teams.
- Growth and exposure to cutting-edge nodes and technologies.
Application Process:
We are looking for immediate to early joiners (15–30 days notice period). If you are passionate about verification and ready to tackle new challenges, we would love to hear from you.
Apply Today: Please send your updated resume to [Confidential Information] or reach out via DM.
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Key Skills
About Company
Skills:
Real Number Modeling, Verification Coverage Analysis, coverage analysis, Cadence Xcelium, Mixed-Signal Testbench Development, DAC Verification, Root-Cause Analysis, Mixed-Signal Waveform Analysis, PLL Verification, Analog Behavioral Modeling, Mixed-Signal Behavioral Models, Mixed-Signal Simulation, Simulation Debugging, ADC Verification, Regression Debugging, Mixed-Signal Interfaces, Verilog-AMS, AMS Verification, Cadence Virtuoso, AMS Verification Methodology, Cadence ADE Assembler
Skills:
Tcl Scripting, Unix Shell Scripting, Perl, Verilog, System Verilog, Python, Incisive, IMC, constrained randomization, behavioral modelling, metric driven, Uvm, ASIC design methodology, Spectre, System Verilog RNM, xCelium, vManager, assertions, VerilogAMS, mixed signal verification
Skills:
monte carlo , Python, Functional Coverage, power management, Analog Mixed-Signal, Uvm, Assertions, systemverilog, Pvt, Verification Automation, Mixed-Signal Debug, RNM, AMS Verification, Verilog-AMS, Spice, AMS Simulation, PMIC
Skills:
automation, Scripting, SoCs, Real model creation, mixed signal verification fundamentals, PSL SV assertions development, model validation, VerilogA, SV Verilog, environment development, verification planning, Verilog-AMS, verification of Power management IPs, behavioral modelling of analog blocks
Skills:
Python, systemverilog, Analog Mixed-Signal circuits, EDA Tools, Verilog-A, Cadence