Automated Testing, Scripting Languages, systemverilog, Uvm, Verification Planning, Testbench Development, Functional Coverage, Debugging Skills, Signal Processing, FPGA Verification

Perl, Verilog, Python, Cadence Incisive, Xcelium, complex testbenches, Uvm, systemverilog, Synopsys VCS, RTL design concepts, VHDL, formal verification, verification environments, Modelsim

Perl, Python, Tcl, timing calibration, Uvm, DDR5 LPDDR5 verification, error handling, systemverilog, SVA, functional coverage, power-management

Computer Architecture, Shell, Perl, Debugging, Python, formal verification, DDR protocols, Functional Verification, Uvm, systemverilog, Rtl Design

System Verilog, Tcl Scripting, SMMU, Uvm, assertion-based verification, UPF, formal verification, Axi, power-aware verification, coverage-driven testing, SVA, Synopsys Mentor VIPs, CXL 1.1 2.0 3.0, verification methodologies, performance power optimization, random constraint-based testing, PCIe Gen3 Gen4 Gen5 Gen6, Coresight architecture, CHI protocols

C, Verilog, Scripting, coverage closure, verification flows, AI-assisted workflows, RTL testbench debugging, memory hierarchy, AMBA protocols, Uvm, systemverilog

Usb, Vcs, DDR, Pcie, Debugging, Ethernet, System Verilog, Coverage, verification concepts, Xcelium, UVM methodology, Axi, Questa, assertions

Perl, Ovm, Python, Axi, APB, AMBA protocols, Uvm, AHB, systemverilog

Makefile, Perl scripting, Verilog, Oop Concepts, Ruby, System Verilog, Post-silicon debugging, CPU architecture, Verification flows, Rtl Design, Asic Design Verification, JTAG protocols, Digital Design, Debugging firmware, Assembly language programming