Lead Design Verification Engineer
Lead Design Verification Engineer
leadsoc technologies pvt ltd6-10 Years
- Posted 2 hours ago
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Job Description
Lead Design Verification Engineer
Location: Bengaluru
Experience: 6–10 Years
Role Overview
We are looking for a Lead Design Verification Engineer with strong hands-on expertise in DDR5 / LPDDR5 verification to drive verification of high-performance memory interfaces and controllers.
Key Responsibilities
- Own verification planning, environment development, execution, and signoff for DDR5/LPDDR5 IPs.
- Develop and enhance SystemVerilog/UVM verification environments.
- Verify DDR5/LPDDR5 protocol, controller functionality, initialization, training, timing, and error scenarios.
- Develop UVM sequences, monitors, scoreboards, checkers, assertions, and functional coverage.
- Drive constrained-random, directed, stress, and corner-case testing.
- Debug complex RTL, protocol, timing, and simulation failures.
- Drive coverage closure, regression infrastructure, and verification signoff.
- Collaborate with RTL, architecture, firmware, PHY, and system validation teams.
- Mentor engineers and drive verification methodology improvements.
Core Technical Skills
- 6–10 years of Design Verification experience.
- Strong hands-on expertise in DDR5 / LPDDR5 verification.
- Expert knowledge of SystemVerilog, UVM, SVA, and functional coverage.
- Strong understanding of DDR protocols, memory controller architecture, initialization and training flows.
- Experience with timing, calibration, power-management, error handling, and corner-case scenarios.
- Strong debug and root-cause analysis skills.
- Proficiency in Python/Perl/Tcl for verification automation.
- Experience with DDR PHY verification, VIP, emulation, or FPGA prototyping is a plus.
Ideal Profile: A hands-on verification lead who can drive DDR5/LPDDR5 verification from strategy and UVM development through coverage closure and signoff, while providing strong technical leadership to the team.
More Info
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Key Skills
About Company
Skills:
DDR, Usb, Pcie, Ethernet, SV, CXL, Uvm
Skills:
PCS, Perl, Python, Tcl, reusable verification infrastructure, PHY link protocols, UVM environment development, high-speed interface verification, Uvm, systemverilog, Ethernet MAC, functional coverage closure, Ethernet protocol compliance verification, packet processing, complex protocol debug, SerDes controller validation, SVA, error handling
Skills:
Unix, Makefile, Shell, Linux, Perl, Verilog, automation, Python, Scripting, System Verilog, Synthesis, front-end flows, ip design, wireless DSP, high-speed design techniques, VHDL
Skills:
Tcl Scripting, Doors, Knowledge of Hardware Board and different components like ADC DAC Serial Memory, DO-254 development process, Electronics Electrical Engineering, Hardware system design knowledge of digital logic, RTL development using VHDL, FPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim Questasim, FPGA Synthesis Place and Route, Developing timing constraints solving CDC issues timing analysis and timing closures for FPGA, Requirement analysis and validation, Different bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAG, FPGA design tools like Libero
Skills:
Test Case Creation, Shell, Perl, Python, Advanced Debugging skills, Uvm, testbench development, coverage-driven verification, Computer Architecture concepts, Formal Verification techniques, Functional Verification, Rtl Design