Design Verification Engineer
Design Verification Engineer
HCL TechBee7-10 Years
- Posted an hour ago
- Be among the first 10 applicants
Job Description
Looking for a Design Verification Engineer with 7-10 years of ASIC/SoC verification experience, strong expertise in UVM, Formal Verification, SystemVerilog/Verilog, verification environment development, debugging, and scripting (Python/Perl)
Mandatory Skills
- 7 to 10 years of experience in Design Verification (DV) for ASIC/SoC
- Strong hands-on experience in UVM (Universal Verification Methodology)
- Experience in Formal Verification
- Strong knowledge of Verilog/SystemVerilog or VHDL
- Experience in developing and debugging complex testbenches and verification environments
- Strong understanding of RTL design concepts
- Experience with simulation tools such as: Synopsys VCS,Cadence Incisive/Xcelium,ModelSim,
- Scripting experience in Python or Perl
- Strong debugging and root cause analysis skills
Preferred Skills
- Experience with formal verification tools
- Team leadership or mentoring experience
- ASIC/SoC verification at block and subsystem level
- Code reviews and verification methodology improvements
More Info
Key Skills
Cadence Incisive
Xcelium
complex testbenches
Synopsys VCS
RTL design concepts
verification environments
About Company
Skills:
C, Pcie, Perl, Python, Tcl, ONFI, LPDDR, NAND
Skills:
Automated Testing, Scripting Languages, systemverilog, Uvm, Verification Planning, Testbench Development, Functional Coverage, Debugging Skills, Signal Processing, FPGA Verification
Early Applicant
Skills:
Perl, Python, Tcl, timing calibration, Uvm, DDR5 LPDDR5 verification, error handling, systemverilog, SVA, functional coverage, power-management
Skills:
Computer Architecture, Shell, Perl, Debugging, Python, formal verification, DDR protocols, Functional Verification, Uvm, systemverilog, Rtl Design
Skills:
System Verilog, Tcl Scripting, SMMU, Uvm, assertion-based verification, UPF, formal verification, Axi, power-aware verification, coverage-driven testing, SVA, Synopsys Mentor VIPs, CXL 1.1 2.0 3.0, verification methodologies, performance power optimization, random constraint-based testing, PCIe Gen3 Gen4 Gen5 Gen6, Coresight architecture, CHI protocols