Design Verification Engineer
- Posted a month ago
- Be among the first 10 applicants
Job Description
Looking for a Design Verification Engineer with 7-10 years of ASIC/SoC verification experience, strong expertise in UVM, Formal Verification, SystemVerilog/Verilog, verification environment development, debugging, and scripting (Python/Perl)
Mandatory Skills
- 7 to 10 years of experience in Design Verification (DV) for ASIC/SoC
- Strong hands-on experience in UVM (Universal Verification Methodology)
- Experience in Formal Verification
- Strong knowledge of Verilog/SystemVerilog or VHDL
- Experience in developing and debugging complex testbenches and verification environments
- Strong understanding of RTL design concepts
- Experience with simulation tools such as: Synopsys VCS,Cadence Incisive/Xcelium,ModelSim,
- Scripting experience in Python or Perl
- Strong debugging and root cause analysis skills
Preferred Skills
- Experience with formal verification tools
- Team leadership or mentoring experience
- ASIC/SoC verification at block and subsystem level
- Code reviews and verification methodology improvements
More Info
Key Skills
Xcelium
Cadence Incisive
complex testbenches
Synopsys VCS
RTL design concepts
verification environments
About Company
Skills:
C, C++, Vcs, Debugging, RTL simulation, on-chip bus protocols, Xcelium, Uvm, systemverilog, SoC-level verification, AMBA, Axi, APB, Questa, AHB, functional coverage
Skills:
bandwidth management , Machine Learning, Artificial Intelligence, SystemVerilog Assertions, Specman E, Debug, formal tools, IP subsystem SoCs, congestion control, AI ML accelerators, systemverilog, memory system architecture, vector processing units, ASIC standard interfaces, packet processing, Verification, Universal Verification Methodology
Skills:
Usb, Mac, Pcie, Perl, Ethernet, Shell scripting, System Verilog, Python, Tcl, AHB-Lite, Uvm, AMBA, Axi, APB
Skills:
Fpga, Usb, Perl, Pcie, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, MIPI, formal verification, Test Bench, transaction level modeling, AXI4
Skills:
Tcl Scripting, Unix Shell Scripting, Perl, Verilog, System Verilog, Debugging, Incisive, IMC, analog mixed signal design, Uvm, advanced verification methodologies, xCelium, vManager, Cadence Virtuoso, test bench development, verification IP, object-oriented programming, Simulation, behavioral modelling, mixed signal verification environment, verification plans, analog blocks